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ADP5586ACBZ-00-R7 数据表(PDF) 39 Page - Analog Devices |
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ADP5586ACBZ-00-R7 数据表(HTML) 39 Page - Analog Devices |
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39 / 44 page  Data Sheet ADP5586 Rev. 0 | Page 39 of 44 PIN_CONFIG_B, Register 0x3B Table 68. PIN_CONFIG_B Bit Descriptions Bits Bit Name Access Description [7:5] Reserved Reserved Reserved. 4 C4_CONFIG Read/write 0 = GPIO 11. 1 = Column 4. 3 C3_CONFIG Read/write 0 = GPIO 10. 1 = Column 3. 2 C2_CONFIG Read/write 0 = GPIO 9. 1 = Column 2. 1 C1_CONFIG Read/write 0 = GPIO 8 (see C1_EXTEND_CFG in Table 69 for alternate configuration, PULSE_GEN_2). 1 = Column 1. 0 C0_CONFIG Read/write 0 = GPIO 7 (see C0_EXTEND_CFG in Table 69 for alternate configuration, PULSE_GEN_1). 1 = Column 0. PIN_CONFIG_C, Register 0x3C Table 69. PIN_CONFIG_C Bit Descriptions Bits Bit Name Access Description 7 PULL_SELECT Read/write 0 = 300 kΩ resistor used for row pull-up during key scanning. 1 = 100 kΩ resistor used for row pull-up during key scanning. 6 C0_EXTEND_CFG Read/write 0 = C0 remains configured as GPIO 7. 1 = C0 reconfigured as PULSE_GEN_1 output. 5 R4_EXTEND_CFG Read/write 0 = R4 remains configured as GPIO 5. 1 = R4 reconfigured as RESET_OUT output. 4 C1_EXTEND_CFG Read/write 0 = C1 remains configured as GPIO 8. 1 = C1 reconfigured as PULSE_GEN_2 output. 3 R3_EXTEND_CFG Read/write 0 = R3 remains configured as GPIO 4. 1 = R3 reconfigured as LC input for the logic block. [2:1] Reserved Reserved Reserved. 0 R0_EXTEND_CFG Read/write 0 = R0 remains configured as GPIO 1. 1 = R0 reconfigured as LY output from the logic block. GENERAL_CFG, Register 0x3D Table 70. GENERAL_CFG Bit Descriptions Bits Bit Name Access Description 7 OSC_EN Read/write 0 = disables internal 800 kHz oscillator. 1 = enables internal 800 kHz oscillator. [6:5] OSC_FREQ[1:0] Read/write Sets the input clock frequency fed from the base 800 kHz oscillator to the digital core. Slower frequencies result in less quiescent current, but key and GPI scan times increase. 00 = 50 kHz. 01 = 100 kHz. 10 = 200 kHz. 11 = 400 kHz. [4:3] Reserved Reserved Reserved. 2 SW_RESET Read/write Software reset. Set to 1 to reset the ADP5586. This function is similar to bringing RST low, then high. Wait at least 200 μs before reprogramming the device. 1 INT_CFG Read/write Configures the behavior of the INT pin if the user tries to clear it while an interrupt is pending. 0 = INT pin remains asserted if an interrupt is pending. 1 = INT pin deasserts for 50 μs and reasserts if an interrupt is pending. 0 RST_CFG Read/write Configures the response of the ADP5586 to the RST pin and the SW_RESET bit. 0 = the ADP5586 resets if RST is low. 1 = the ADP5586 does not reset if RST is low. |
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