ADP5586ACBZ-00-R7 datasheet(8/44 Pages) AD

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ADP5586

Data Sheet

Rev. 0 | Page 8 of 44

DEVICE ENABLE

When sufficient voltage is applied to VDD and the RST pin is

driven with a logic high level, the ADP5586 starts up in standby

mode with all settings at default. The user can configure the

device via the I2C interface. When the RST pin is low, the

ADP5586 enters a reset state and all settings return to default.

The RST pin features a debounce filter.

If the ADP5586ACBZ-01-R7 device model is used, the RST pin

acts as an additional row pin (R5). To reset the part without a

reset pin, either bring VDD below the UVLO threshold, or set

the SW_RESET bit to 1 (Register 0x3D, Bit 2).

DEVICE OVERVIEW

The ADP5586 contains 10 multiconfigurable input/output pins.

Each pin can be programmed to enable the device to carry out

its various functions, as follows:



Keypad matrix decoding (five-column by five-row matrix

maximum)



General-purpose I/O expansion (up to 10 inputs/outputs)



Reset generator



Logic function building blocks (up to three inputs and one

output)



Two pulse generators

All 10 input/output pins have an I/O structure as shown in

Figure 5.

I/O

VDD

100kΩ

DEBOUNCE

300kΩ

I/O

DRIVE

Figure 5. I/O Structure

Each I/O can be pulled up with a 100 kΩ or 300 kΩ resistor or

pulled down with a 300 kΩ resistor. For logic output drive, each

I/O has a 5 mA PMOS source and a 10 mA NMOS sink for a push-

pull type output. For open-drain output situations, the 5 mA

PMOS source is not enabled. For logic input applications, each

I/O can be sampled directly or, alternatively, sampled through

a debounce filter.

The I/O structure shown in Figure 5 allows for all GPI and GPO

functions, as well as PWM and clock divide functions. For key

matrix scan and decode, the scanning circuit uses the 100 kΩ or

300 kΩ resistor for pulling up the keypad row pins and the 10 mA

NMOS sinks for grounding the keypad column pins (see the

Key Scan Control section for details about key decoding).

Configuration of the device is carried out by programming an

array of internal registers via the I2C interface. Feedback of device

status and pending interrupts can be flagged to an external

processor by using the INT pin.

The ADP5586 is offered with three feature sets. Table 6 lists

the options that are available for each model of the ADP5586.

Contact your local Analog Devices, Inc., field applications

engineers for availability and/or alternate configurations.

Table 6. Matrix Options by Device Model1

Model

Description

ADP5586ACBZ-00-R7

GPIO pull-down on startup

5-row × 5-column matrix

ADP5586ACBZ-01-R7

Row 5 added to GPIOs

6-row × 5-column matrix

ADP5586ACBZ-03-R7

Alternate I2C address (0x30)

5-row × 5-column matrix

1 Contact Analog Devices for availability of configurations not shown here.

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