WM8952ECSSLASHRV datasheet(44/72 Pages) WOLFSON

部件名	WM8952ECS/RV

功能描述	Mono ADC with Microphone Pre-amplifier

PDF	72 Pages

Scroll/Zoom	100%

制造商	WOLFSON [Wolfson Microelectronics plc]

网页	http://www.wolfsonmicro.com

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44 / 72 page

WM8952

Pre Production

PP, Rev 3.1, June 2011

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)

The WM8952 has an on-chip phase-locked loop (PLL) circuit that can be used to:

•

Generate master clocks for the WM8952 audio functions from another external clock, e.g.

in telecoms applications.

•

Generate an output clock, on GPIO, for another part of the system (derived from an

existing audio master clock).

Table 32 shows the PLL and internal clocking arrangement on the WM8952.

The PLL is enabled or disabled by the PLLEN register bit.

Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are

set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

Management 1

PLLEN

PLL enable

0=PLL off

1=PLL on

Table 32 PLLEN Control Bit

Figure 24 PLL and Clock Select Circuit

WM8952ECS/RV 数据表(PDF) 44 Page - Wolfson Microelectronics plc