 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
WM8952ECS/RV 数据表(PDF) 51 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8952ECS/RV 数据表(HTML) 51 Page - Wolfson Microelectronics plc |
|
|
51 / 72 page  Pre Production WM8952 w PP, Rev 3.1, June 2011 51 3-WIRE SERIAL CONTROL MODE In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits. Figure 28 3-Wire Serial Control Interface READBACK IN 3-WIRE MODE The following two timing diagrams are also supported. Figure 29 Alternative 3-Wire Serial Control Timing Figure 30 Alternative 3-Wire Serial Control Timing A limited number of Readback addresses are provided to enable ALC operation to be monitored and to establish the identity and revision of the device. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 Software Reset 15:0 CHIP_ID Readback the CHIP ID R1 Power Management 1 2:0 DEVICE_REVI SON Readback the DEVICE_REVISON Table 42 Readback Registers |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
