WM8952ECSSLASHRV datasheet(12/72 Pages) WOLFSON

12 / 72 page

WM8952

Pre Production

PP, Rev 3.1, June 2011

Test Conditions

DVDD=1.8V, AVDD= 3.3V, DGND=AGND =0V, TA=+25

oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise

stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

FRAME propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DVDD=1.8V, AVDD=3.3V, DGND=AGND =0V, TA=+25

oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise

stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

81.38

BCLK pulse width high

tBCH

32.55

BCLK pulse width low

tBCL

32.55

FRAME set-up time to BCLK rising edge

tLRSU

FRAME hold time from BCLK rising edge

tLRH

ADCDAT propagation delay from BCLK falling edge

tDD

Note:

BCLK period should always be greater than or equal to MCLK period.

WM8952ECS/RV 数据表(PDF) 12 Page - Wolfson Microelectronics plc

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