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WM8952ECS/RV 数据表(PDF) 54 Page - Wolfson Microelectronics plc |
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WM8952ECS/RV 数据表(HTML) 54 Page - Wolfson Microelectronics plc |
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54 / 72 page ![]() WM8952 Pre Production w PP, Rev 3.1, June 2011 54 POWER MANAGEMENT VMID The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 1:0 VMIDSEL 00 Reference string impedance to VMID pin (determines startup time): 00=off (open circuit) 01=50kΩ 10=250kΩ 11=5kΩ (for fastest startup) Table 43 VMID Impedance Control BIASEN REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 3 BIASEN 0 Analogue amplifier bias control 0=Disabled 1=Enabled Table 44 BIASEN Control ESTIMATED SUPPLY CURRENTS When either the ADC is enabled it is estimated that approximately 4mA will be drawn from DVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DVDD. Table 45 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT AVDD CURRENT (MILLIAMPS) PLLEN 1.4mA (with clocks applied) MICBEN 0.5mA BIASEN 0.3mA BUFIOEN 0.1mA VMIDSEL 5K=>0.3mA, less than 0.1mA for 50k/250k BOOSTEN 0.2mA INPPGAEN 0.2mA ADCEN 2.6mA Table 45 AVDD Supply Current |
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