ADRF6518ACPZ-R7 datasheet(32/36 Pages) AD

32 / 36 page

ADRF6518

Preliminary Technical Data

Rev. PrA | Page 32 of 36

Components

Function

Default Conditions

To bypass the T1 and T2 baluns for differential interfacing, remove

the balun interfacing resistors, R31, R32, R47, R48, R49, and R50, and

populate R43, R44, R45, and R46 with 0 Ω resistors.

T3, T4, C19 to C24,

R5, R6

R19, R20,

R35 to R42

Output interface. The OPP1, OPM1_SE, OPP2, and OPM2_SE output

SMAs are used to obtain differential signals from the part when the

output baluns are bypassed. Using OPM1_SE, OPM2_SE, and the

baluns, the user can obtain single-ended output signals. The default

configuration of the evaluation board is for single-ended operation.

T3 and T4 are 8:1 impedance ratio baluns that transform a

differential signal in a 400 Ω system into a single-ended signal in a

50 Ω system.

To bypass the T3 and T4 baluns for differential interfacing, remove

the balun interfacing resistors, R19, R20, R35, R36, R41, and R42, and

populate R37, R38, R39, and R40 with 0 Ω resistors.

R5 and R6 can be populated with an impedance of at least 400 Ω to

terminate the output in differential applications.

T3, T4 = Pulse Electronics

CX2049LNL

C19 to C24 = 0.1 µF (Size 0402)

R5, R6 = open (size 0402)

R19, R20, R35, R36, R41, R42 = 0 Ω

(Size 0402)

R37 to R40 = open

(Size 0402)

Enable interface. The ADRF6518 is powered up by applying a logic

high voltage to the ENBL pin (Jumper P2 is connected to VPS).

P2 = installed for enable

P3, R1, R17, R18, R21, R63, C25,

C53, C55, C56

Serial control interface. The digital interface sets the corner

frequency, VGA1/VGA2/VGA3 maximum gains, and the

postamplifier maximum gain using the serial interface via the LE,

CLK, DATA, and SDO pins.

RC filter networks can be populated on the CLK, LE, and DATA lines

to filter the SPI signals. CLK, DATA, and LE signals can be observed

via P3 for debug purposes. Setting C25, C53, and C56 = 330 pF is

recommending for filtering.

P3 = installed

R1 = 0 Ω (Size 0402)

R21 = 10 kΩ (Size 0402)

C25, C53, C55, C56 = open (Size

0402)

R17, R18, R63 = 1 kΩ (Size 0402)

C13, C14

DC offset compensation loop. The dc offset compensation loop is

enabled via the SPI port. When enabled, the C13 and C14 capacitors

are connected to circuit common. The high-pass corner frequency is

expressed as follows:

fHP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF))

C13, C14 = 0.1 µF (Size 0402)

Input common-mode reference. The input common-mode voltage

can be monitored at the VICM pin. If the VICM pin is left open, an

input common-mode voltage must be supplied externally ( DC

coupling mode). If VICM pin is connected to ground, the input

common-mode defaults to VPI/2 (ac coupling mode).

C5 = 0.1 µF (Size 0402)

C18

Output common-mode setpoint. The output common-mode

voltage can be set externally when applied to the VOCM pin. If the

VOCM pin is left open, the output common-mode voltage defaults

to VPS/2.

C18 = 0.1 µF (Size 0402)

C17, C27, C32

Analog gain control. The range of the analog gain pins, VGN1, VGN2,

and VGN3, is from 0 V to 1 V, creating a gain scaling of 30 mV/dB.

C17, C27, C32 = 0.1 µF (Size 0402)

P1, R4, R15, C33, C34

Peak Detector.

P1 = installed

R4 = 0 Ω (Size 0402)

R15, C33, C34 = open (Size 0402)

U1, U2, U3, P5

Cypress Microcontroller, EEPROM, and LDO

U2 = Microchip MICRO24LC64

U3 = Analog Devices

ADP3334ACPZ

U4 = Cypress Semiconductor

CY7C68013A-56LTXC

P5 = Mini USB connector

C35, C36, C40, C41, C42, C44,

C46

3.3 V supply decoupling. Several capacitors are used for decoupling

on the 3.3 V supply.

C35, C36, C40, C41, C42, C44, C46

= 0.1 µF (0402)

C37, C38, C39, C45, C48, C49,

R59, R60, R61, R62, R64, CR2

Cypress and EEPROM components.

C38, C48 = 10 pF (0402)

C37, C39, C45, C49 = 0.1 µF (0402)

R59, R60, R61 = 2 kΩ (0402)

R62, R64 = 100 kΩ (0402)

CR2 = ROHM SML-21OMTT86

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