ADRF6518ACPZ-R7 datasheet(21/36 Pages) AD

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Preliminary Technical Data

ADRF6518

Rev. PrA | Page 21 of 36

THEORY OF OPERATION

The ADRF6518 consists of a matched pair of input VGAs

followed by programmable filters, and then by a cascade of two

variable gain amplifiers and output ADC drivers. The filters can

be bypassed and powered down through the SPI interface for

operation beyond the maximum filter bandwidth. The block

diagram of a single channel is shown in Figure 68.

The programmability of the filter bandwidth and of the prefilter-

ing and postfiltering fixed gains through the SPI interface offers

great flexibility when coping with signals of varying levels in the

presence of noise and large, undesired signals near the desired

band. The entire differential signal chain is dc-coupled with

flexible interfaces at the input and output. The bandwidth and

gain setting controls for the two channels are shared, ensuring

close matching of their magnitude and phase responses. The

ADRF6518 can be fully disabled through the ENBL pin.

Figure 68. Signal Path Block Diagram for a Single Channel of the ADRF6518

Filtering and amplification are fundamental operations in any

signal processing system. Filtering is necessary to select the

intended signal while rejecting out-of-band noise and

interferers. Amplification increases the level of the desired

signal to overcome noise added by the system. When used

together, filtering and amplification can extract a low level

signal of interest in the presence of noise and out-of-band

interferers. Such analog signal processing alleviates the

requirements on the analog, mixed signal, and digital

components that follow.

INPUT VGAs

The input VGAs provide a convenient interface to the sensitive

filter sections that follow. They are designed to have a low noise

figure and high linearity. The combination of analog gain control

and digital gain settings allow a wide range of input signal levels

to be conditioned to drive the filters at up to 2 V p-p amplitude.

The VGAs set a differential input impedance of 400 Ω.

The baseband input signal can be ac-coupled or dc-coupled via

Pin 7 selection. When the signal is dc-coupled, wide input

common-mode voltage is supported by having an optional 5 V

supply on Pin 8, VPI. The default common-mode voltage is

VPI/2, which is available on the dual function Pin 7, VICM/AC,

to set the output common-mode voltage of the driving circuit.

However, this is optional and input common-mode can be

independently set within the supported range. For a 3.3 V

supply on VPI, the input common mode can range from 1.35 V

to 1.95 V, while maintaining a 5 V p-p input level at >60 dBc

HD2 and HD3. For a 5 V supply on VPI, the input common-mode

range extends to 1.35 V to 3.1 V. Extra current is drawn from the

VPI supply to support an input common mode greater than the

midvalue of the main 3.3 V supply, that is, VPS/2.

The VICM/AC voltage is not buffered and must be sensed at a

high impedance point to prevent it from being loaded down.

When the baseband input signal is ac-coupled, pull the VICM/AC

pin low to activate the internal bias for the input stage.

The input VGAs have analog gain control of 24 dB, followed

by a digital gain settings of 9 dB, 12 dB, or 15 dB, selectable

through the SPI (see the Register Map and Codes section). The

VGAs are based on the Analog Devices, Inc., patented X-AMP®

architecture, consisting of tapped 24 dB attenuators, followed by

programmable gain amplifiers. The X-AMP architecture gener-

ates a continuous linear-in-dB monotonic gain response with

low ripple. The analog gain of the VGA sections are controlled

through the high impedance VGN1 pin with an accurate slope

of 30 mV/dB. Adjust the VGA analog gain through an AGC

mechanism, such that 2 V p-p at the output of the first VGA is

not exceeded. If, however, the input signal is small enough, the

first VGA can be set at full gain for best noise figure (NF) perfor-

mance and gain control achieved in the second or third VGA.

Driving ADRF6518 Single-Ended

The input structure of the ADRF6518 is designed for differen-

tial drive. However, with some performance degradation, it can

be driven single ended, especially at low bandwidth signals. See

the Applications Information section for guidance on single-

ended drive.

PEAK DETECTOR

To measure the signal level at the critical interface of the VGA1

output and the programmable filter input, a peak detector has

been implemented. The peak detector simultaneously measures

both channels at the VGA1 output and reports the bigger of the

two at the VPK pin. The on-chip holding capacitor and negligi-

ble leakage at the internal node ensure a large droop time of the

order of a millisecond, which is a function of the peak voltage as

well. Bigger peak voltage results in longer droop time. The droop

time can be adjusted down by placing a resistor between the

RAVG and VPOS pins. Typical values of RAVG can range from

1 MΩ to 1 kΩ. As the RAVG resistor value is reduced, the peak

voltage, VPK, appears as an envelope output. The peak detector

has the attack bandwidth of 100 MHz.

The peak detector can be used in an AGC loop to set the appropri-

ate signal level at the filter input. For such an implementation,

Filter VPK appropriately, considering that it is a peak hold

output. A high pulse of 25 ns or longer duration applied to the

SDO/RST dual function pin resets the VPK voltage to 0 V by

discharging the internal holding capacitor.

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