STM32F103C8T7 datasheet(70/105 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F103x8, STM32F103xB

70/105

Doc ID 13587 Rev 15

5.3.16

Communications interfaces

2C interface characteristics

The STM32F103xx performance line I

2C interface meets the requirements of the standard

2C communication protocol with the following restrictions: the I/O pins SDA and SCL are

mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected

between the I/O pin and VDD is disabled, but is still present.

The I

2C characteristics are described in Table 40. Refer also to Section 5.3.12: I/O current

injection characteristics for more details on the input/output alternate function characteristics

(SDA and SCL).

Table 40.

I2C characteristics

Symbol

Parameter

Standard mode I2C(1)

Guaranteed by design, not tested in production.

Fast mode I2C(1)(2)

fPCLK1 must be at least 2 MHz to achieve standard mode I

2C frequencies. It must be at least 4 MHz to

achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C

fast mode clock.

Unit

Min

Max

Min

Max

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

900(3)

The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL

signal.

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

20 + 0.1Cb

300

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

th(STA)

Start condition hold time

4.0

0.6

µs

tsu(STA)

Repeated Start condition

setup time

4.7

0.6

tsu(STO)

Stop condition setup time

4.0

0.6

μs

tw(STO:STA)

Stop to Start condition time

(bus free)

4.7

1.3

μs

Capacitive load for each bus

line

400

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