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OMAP3530ECBC72 数据表(PDF) 37 Page - Texas Instruments

部件名 OMAP3530ECBC72
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBC72 数据表(HTML) 37 Page - Texas Instruments

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OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP
PIN NAME
MODE [4]
TYPE [5]
BALL
BALL
RESET REL. POWER [9]
HYS [10]
BUFFER
PULLUP
IO CELL [13]
BOTTOM [1] [2]
[3]
RESET
RESET REL. MODE [8]
STRENG TH /DOWN
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
hsusb3_tll_n 5
IO
xt
mm3_rxdm
6
IO
safe_mode
7
AF6
NA
mcbsp3_dx
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart2_cts
1
I
gpio_140
4
IO
hsusb3_tll_
5
IO
data4
safe_mode
7
AE6
NA
mcbsp3_dr
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart2_rts
1
O
gpio_141
4
IO
hsusb3_tll_
5
IO
data5
safe_mode
7
AF5
NA
mcbsp3_
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
clkx
uart2_tx
1
O
gpio_142
4
IO
hsusb3_tll_
5
IO
data6
safe_mode
7
AE5
NA
mcbsp3_fsx
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart2_rx
1
I
gpio_143
4
IO
hsusb3_tll_
5
IO
data7
safe_mode
7
AB26
NA
uart2_cts
0
I
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_dx
1
IO
gpt9_pwm_e 2
IO
vt
gpio_144
4
IO
safe_mode
7
AB25
NA
uart2_rts
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_dr
1
I
gpt10_pwm_ 2
IO
evt
gpio_145
4
IO
safe_mode
7
AA25
NA
uart2_tx
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_
1
IO
clkx
gpt11_pwm
2
IO
_evt
gpio_146
4
IO
safe_mode
7
AD25
NA
uart2_rx
0
I
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_fsx
1
IO
gpt8_pwm_e 2
IO
vt
gpio_147
4
IO
safe_mode
7
AA8
NA
uart1_tx
0
O
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_148
4
IO
safe_mode
7
AA9
NA
uart1_rts
0
O
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
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TERMINAL DESCRIPTION
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