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OMAP3530ECBC72 数据表(PDF) 73 Page - Texas Instruments

部件名 OMAP3530ECBC72
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBC72 数据表(HTML) 73 Page - Texas Instruments

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OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2-3. Ball Characteristics (CUS Pkg.) (continued)
BALL
BALL TOP [2] PIN NAME [3] MODE [4]
TYPE [5]
BALL RESET BALL RESET RESET REL.
POWER [9]
HYS [10]
BUFFER
PULLUP
BOTTOM [1]
STATE [6]
REL. STATE
MODE [8]
STRENG TH
/DOWN TYPE
[7]
(mA) [11]
[12]
mcbsp4_fsx
2
IO
gpt8_pwm_evt 3
IO
gpio_58
4
IO
safe_mode
7
W2
gpmc_clk
0
O
L
0
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_59
4
IO
safe_mode
7
F1
gpmc_nadv_al 0
O
0
0
0
vdds_ mem
No
4
NA
LVCMOS
e
F2
gpmc_noe
0
O
1
1
0
vdds_ mem
No
4
NA
LVCMOS
G3
gpmc_nwe
0
O
1
1
0
vdds_ mem
No
4
NA
LVCMOS
K5
gpmc_nbe0_cl 0
O
L
0
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
e
gpio_60
4
IO
safe_mode
7
L1
gpmc_nbe1
0
O
L
L
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_61
4
IO
safe_mode
7
E1
gpmc_nwp
0
O
L
0
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_62
4
IO
safe_mode
7
C1
gpmc_wait0
0
I
H
H
0
vdds_ mem
Yes
NA
PU/ PD
LVCMOS
C2
gpmc_wait3
0
I
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
sys_
1
I
ndmareq1
gpio_65
4
IO
safe_mode
7
G22
dss_pclk
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_66
4
IO
safe_mode
7
E22
dss_hsync
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_67
4
IO
safe_mode
7
F22
dss_vsync
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_68
4
IO
safe_mode
7
J21
dss_acbias
0
O
L
L
7
vdds
Yes
8
PU/ PD
LVCMOS
gpio_69
4
IO
safe_mode
7
AC19
dss_data0
0
IO
L
L
7
vdds
No
4
PU/ PD
LVCMOS
uart1_cts
2
I
gpio_70
4
IO
safe_mode
7
AB19
dss_data1
0
IO
L
L
7
vdds
No
4
PU/ PD
LVCMOS
uart1_rts
2
O
gpio_71
4
IO
safe_mode
7
AD20
dss_data2
0
IO
L
L
7
vdds
No
4
PU/ PD
LVCMOS
gpio_72
4
IO
safe_mode
7
AC20
dss_data3
0
IO
L
L
7
vdds
No
4
PU/ PD
LVCMOS
gpio_73
4
IO
safe_mode
7
AD21
dss_data4
0
IO
L
L
7
vdds
No
4
PU/ PD
LVCMOS
uart3_rx_ irrx
2
I
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TERMINAL DESCRIPTION
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