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OMAP3530ECBC72 数据表(PDF) 96 Page - Texas Instruments |
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OMAP3530ECBC72 数据表(HTML) 96 Page - Texas Instruments |
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96 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 2-5. External Memory Interfaces – GPMC Signals Description (continued) SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM [1] [3] BOTTOM TOP (CBC Pkg.) [4] (CBC Pkg.) [5] BOTTOM PIN (CBB (CBB (CUS MULTIPLEXING Pkg.) [4] Pkg.) [5] Pkg.) [4] [6] gpmc_ncs6 GPMC Chip Select bit 6 O P8 NA B5 NA F3 NA gpmc_ncs7 GPMC Chip Select bit 7 O N8 NA C5 NA G4 NA gpmc_io_dir GPMC IO direction control for use O N8 NA C5 NA G4 NA with external transceivers gpmc_clk GPMC clock O T4 W2 N1 L1 W2 NA gpmc_nadv_ale Address Valid or Address Latch O F3 W1 AD10 AA9 F1 NA Enable gpmc_noe Output Enable O G2 V2 N2 L2 F2 NA gpmc_nwe Write Enable O F4 V1 M1 K1 G3 NA gpmc_nbe0_cle Lower Byte Enable. Also used for O G3 AC12 K2 FT(1) K5 NA Command Latch Enable gpmc_nbe1 Upper Byte Enable O U3 NA J1 NA L1 NA gpmc_nwp Flash Write Protect O H1 AB10 AC6 Y5 E1 NA gpmc_wait0 External indication of wait I M8 AB12 AC11 Y10 C1 NA gpmc_wait1 External indication of wait I L8 AC10 AC8 Y8 NA NA gpmc_wait2 External indication of wait I K8 NA B3 NA NA NA gpmc_wait3 External indication of wait I J8 NA C6 NA C2 NA (1) FT indicates "Feed-Through. For more information, refer to Section 2.5.10. Table 2-6. External Memory Interfaces – SDRC Signals Description SIGNAL DESCRIPTION TYPE(1) BALL BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM NAME BOTTOM (CBB Pkg.) (CBC Pkg.) (CBC Pkg.) (CUS Pkg.) (CBB Pkg.) sdrc_d0 SDRAM data bit 0 IO D6 J2 NA D1 D7 sdrc_d1 SDRAM data bit 1 IO C6 J1 NA G1 C5 sdrc_d2 SDRAM data bit 2 IO B6 G2 NA G2 C6 sdrc_d3 SDRAM data bit 3 IO C8 G1 NA E1 B5 sdrc_d4 SDRAM data bit 4 IO C9 F2 NA D2 D9 sdrc_d5 SDRAM data bit 5 IO A7 F1 NA E2 D10 sdrc_d6 SDRAM data bit 6 IO B9 D2 NA B3 C7 sdrc_d7 SDRAM data bit 7 IO A9 D1 NA B4 B7 sdrc_d8 SDRAM data bit 8 IO C14 B13 NA A10 B11 sdrc_d9 SDRAM data bit 9 IO B14 A13 NA B11 C12 sdrc_d10 SDRAM data bit 10 IO C15 B14 NA A11 B12 sdrc_d11 SDRAM data bit 11 IO B16 A14 NA B12 D13 sdrc_d12 SDRAM data bit 12 IO D17 B16 NA A16 C13 sdrc_d13 SDRAM data bit 13 IO C17 A16 NA A17 B14 sdrc_d14 SDRAM data bit 14 IO B17 B19 NA B17 A14 sdrc_d15 SDRAM data bit 15 IO D18 A19 NA B18 B15 sdrc_d16 SDRAM data bit 16 IO D11 B3 NA B7 C9 sdrc_d17 SDRAM data bit 17 IO B10 A3 NA A5 E12 sdrc_d18 SDRAM data bit 18 IO C11 B5 NA B6 B8 sdrc_d19 SDRAM data bit 19 IO D12 A5 NA A6 B9 sdrc_d20 SDRAM data bit 20 IO C12 B8 NA A8 C10 sdrc_d21 SDRAM data bit 21 IO A11 A8 NA B9 B10 sdrc_d22 SDRAM data bit 22 IO B13 B9 NA A9 D12 sdrc_d23 SDRAM data bit 23 IO D14 A9 NA B10 E13 sdrc_d24 SDRAM data bit 24 IO C18 B21 NA C21 E15 sdrc_d25 SDRAM data bit 25 IO A19 A21 NA D20 D15 (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). TERMINAL DESCRIPTION 96 Submit Documentation Feedback |
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