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OMAP3530ECBC72 数据表(PDF) 49 Page - Texas Instruments

部件名 OMAP3530ECBC72
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBC72 数据表(HTML) 49 Page - Texas Instruments

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OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2-2. Ball Characteristics (CBC Pkg.) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
NA
D21
sdrc_d28
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
E20
sdrc_d29
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
E21
sdrc_d30
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
G21
sdrc_d31
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
H1
sdrc_dm0
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
A14
sdrc_dm1
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
A4
sdrc_dm2
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
A18
sdrc_dm3
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
C2
sdrc_dqs0
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B15
sdrc_dqs1
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B8
sdrc_dqs2
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
A19
sdrc_dqs3
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
U20
sdrc_ncas
0
O
1
1
0
vdds
No
4
(2)
NA
LVCMOS
NA
B13
sdrc_nclk
0
O
1
1
0
vdds
No
4
(2)
NA
LVCMOS
NA
T21
sdrc_ncs0
0
O
1
1
0
vdds
No
4
(2)
NA
LVCMOS
NA
T20
sdrc_ncs1
0
O
1
1
0
vdds
No
4
(2)
NA
LVCMOS
NA
V21
sdrc_nras
0
O
1
1
0
vdds
No
4
(2)
NA
LVCMOS
NA
Y18
sdrc_nwe
0
O
1
1
0
vdds
No
4
(2)
NA
LVCMOS
AE21
NA
dss_data0
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart1_cts
2
I
gpio_70
4
IO
safe_mode
7
-
AE22
NA
dss_data1
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart1_rts
2
O
gpio_71
4
IO
safe_mode
7
-
AE23
NA
dss_data2
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
gpio_72
4
IO
safe_mode
7
-
AE24
NA
dss_data3
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
gpio_73
4
IO
safe_mode
7
-
AD23
NA
dss_data4
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart3_rx_irrx
2
I
gpio_74
4
IO
safe_mode
7
-
AD24
NA
dss_data5
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart3_tx_irtx
2
O
gpio_75
4
IO
safe_mode
7
-
AC26
NA
dss_data10
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
gpio_80
4
IO
safe_mode
7
-
AD26
NA
dss_data11
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
Submit Documentation Feedback
TERMINAL DESCRIPTION
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