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STM32F030C8 数据表(PDF) 71 Page - STMicroelectronics

部件名 STM32F030C8
功能描述  Value-line ARM-based 32-bit MCU with 16 to 64-KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation
PDF  88 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F030C8 数据表(HTML) 71 Page - STMicroelectronics

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STM32F030x4 STM32F030x6 STM32F030x8
Electrical characteristics
73
Table 57. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
-
18
MHz
Slave mode
-
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
-
6
ns
tsu(NSS)
(1)
NSS setup time
Slave mode
4Tpclk
-
ns
th(NSS)
(1)
NSS hold time
Slave mode
2Tpclk + 10
-
tw(SCKH)
(1)
tw(SCKL)
(1)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 -2
Tpclk/2 + 1
tsu(MI)
(1)
tsu(SI)
(1)
Data input setup time
Master mode
4
-
Slave mode
5
-
th(MI)
(1)
Data input hold time
Master mode
4
-
th(SI)
(1)
Slave mode
5
-
ta(SO)
(1)(2)
Data output access time
Slave mode, fPCLK = 20 MHz
0
3Tpclk
tdis(SO)
(1)(3)
Data output disable time
Slave mode
0
18
tv(SO)
(1)
Data output valid time
Slave mode (after enable edge)
-
22.5
tv(MO)
(1)
Data output valid time
Master mode (after enable edge)
-
6
th(SO)
(1)
Data output hold time
Slave mode (after enable edge)
11.5
-
th(MO)
(1)
Master mode (after enable edge)
2
-
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
25
75
%
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the
data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the
data in Hi-Z



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