PCF8563PSLASHF4 datasheet(28/50 Pages) NXP

28 / 50 page

PCF8563

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Product data sheet

Rev. 10 — 3 April 2012

28 of 50

NXP Semiconductors

PCF8563

Real-time clock/calendar

9.6 Interface watchdog timer

During read/write operations, the time counting circuits are frozen. To prevent a situation

where the accessing device becomes locked and does not clear the interface, the

PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s

from the time a valid slave address is transmitted, then the PCF8563 will automatically

clear the interface and allow the time counting circuits to continue counting. The watchdog

will trigger between 1 s and 2 s after receiving a valid slave address. Each time the

watchdog period is exceeded, 1 s will be lost from the time counters.

The watchdog is implemented to prevent the excessive loss of time due to interface

access failure e.g. if main power is removed from a battery backed-up system during an

interface access.

a. Correct data transfer: read or write

b. Incorrect data transfer; read or write

Fig 22. Interface watchdog timer

013aaa420

SLAVE ADDRESS

running

time

counters

WD timer

data

WD timer tracking

time counters frozen

running

DATA

t < 1 s

DATA

STOP

START

013aaa421

SLAVE ADDRESS

running

time

counters

WD timer

data

WD timer tracking

time counters frozen

running

DATA

1 s < t < 2 s

DATA

START

data transfer fail

WD trips

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