JS28F512P30TFA datasheet(5/86 Pages) MICRON

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Datasheet

Sept 2012

Order Number:208042-0

P30-65nm

1.0

Functional Description

1.1

Introduction

This document provides information about the Numonyx® AxcellTM P30-65nm Flash

memory and describes its features, operations, and specifications.

P30-65nm is the latest generation of Numonyx® AxcellTM P30 Flash memory to the

embedded flash market segment, offered in 64-Mbit up through 2-Gbit. This document

covers specifically 512-Mbit, 1-Gbit and 2-Gbit product information. Benefits include

more density in less space, high-speed interface on TSOP package, and support for

code and data storage. Features include high-performance synchronous-burst read

mode, a dramatical improvement in buffer program time through larger buffer size, fast

asynchronous access times, low power, flexible security options, and two industry-

standard package choices.

P30-65nm is manufactured using Numonyx® 65nm process technology.

1.2

Overview

P30-65nm device provides high performance on a 16-bit data bus. Individually erasable

memory blocks are sized for optimum code and data storage. Upon initial power-up or

return from reset, the device defaults to asynchronous page-mode read. Configuring

the Read Configuration Register (RCR) enables synchronous burst-mode reads. In

synchronous burst mode, output data is synchronized with a user-supplied clock signal.

A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates

technology that enables fast buffer program and erase operations. The device features

a 512-word buffer to enable optimum programming performance, which can improve

system programming throughput time significantly to 1.46MByte/s.

Designed for low-voltage systems, the P30-65nm device supports read operations with

VCC at 1.8V, and erase and program operations with VPP at 1.8V or 9.0V. Buffered

Enhanced Factory Programming provides the fastest flash array programming

performance with VPP at 9.0V, which increases factory throughput. With VPP at 1.8V,

VCC and VPP can be tied together for a simple, ultra low power design. In addition to

voltage flexibility, a dedicated VPP connection provides complete data protection when

VPP ≤ VPPLK.

The Command User Interface is the interface between the system processor and all

internal operations of the device. An internal Write State Machine automatically

executes the algorithms and timings necessary for block erase and program. A Status

A device command sequence invokes program and erase automation. Each erase

operation erases one block. The Erase Suspend feature allows system software to

pause an erase cycle to read or program data in another block. Program Suspend

allows system software to pause programming to read other locations.

P30-65nm OTP Register allows unique flash device identification that can be used to

increase system security. The individual Block Lock feature provides zero-latency block

locking and unlocking. The P30-65nm device adds enhanced protection via Password

Access; this new feature allows write and/or read access protection of user-defined

blocks. In addition, the P30-65nm device also has backward compatible One-Time

Programmable (OTP) permanent block locking security feature.

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