JS28F512P30TFA datasheet(52/86 Pages) MICRON

52 / 86 page

P30-65nm

Datasheet

Sept 2012

Order Number: 208042-0

Synchronous Specifications (Easy BGA)(5)

R301

tAVCH/L

Address setup to CLK

1,6

R302

tVLCH/L

ADV# low setup to CLK

R303

tELCH/L

CE# low setup to CLK

R304

tCHQV/tCLQV

CLK to output valid

R305

tCHQX

Output hold from CLK

R306

tCHAX

Address hold from CLK

1,4,6

R307

tCHTV

CLK to WAIT valid

1,6

R311

tCHVL

CLK valid to ADV# Setup

R312

tCHTX

WAIT hold from CLK

1,6

Notes:

See

Figure 15, “AC Input/Output Reference Waveform” on page 49 for timing measurements and max

allowable input slew rate.

OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.

Sampled, not 100% tested.

Address hold in synchronous burst read mode is tCHAX or tVHAX, whichever timing specification is satisfied first.

Synchronous burst read mode is not supported with TTL level inputs.

Applies only to subsequent synchronous reads.

Figure 18: Asynchronous Single-Word Read (ADV# Low)

Table 25: AC Read Specifications - (Sheet 2 of 2)

Num

Symbol

Parameter

Min

Max

Unit

Notes

R17

R15

Address[A]

ADV#[V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

RST# [P]

JS28F512P30TFA 数据表(PDF) 52 Page - Micron Technology

JS28F512P30TFA 数据表(HTML) 52 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

数据表下载