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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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JS28F512P30TFA 数据表(PDF) 6 Page - Micron Technology |
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JS28F512P30TFA 数据表(HTML) 6 Page - Micron Technology |
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6 / 86 page  P30-65nm Datasheet Sept 2012 6 Order Number: 208042-0 6 1.3 Virtual Chip Enable Description (2-Gbit) The P30-65nm device employs a Virtual Chip Enable to combine two 1-Gbit dies with a common chip enable, CE#, for Easy BGA packages. Address A27 is then used to select between the die pair with CE# asserted. When chip enable is asserted and A27 is low (VIL), the lower flash die is selected; when chip enable is asserted and A27 is high (VIH), the upper flash die is selected. Table 1: Flash Die Virtual Chip Enable Truth Table for 2-Gbit (1-Gbit/1-Gbit) Devices Die Selected CE# A27 Lower Flash Die L L Upper Flash Die L H |
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