数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

AD7654ASTZ 数据表(PDF) 5 Page - Analog Devices

部件名 AD7654ASTZ
功能描述  16-Bit, 500 kSPS PulSAR짰 Dual, 2-Channel, Simultaneous Sampling ADC
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7654ASTZ 数据表(HTML) 5 Page - Analog Devices

  AD7654ASTZ Datasheet HTML 1Page - Analog Devices AD7654ASTZ Datasheet HTML 2Page - Analog Devices AD7654ASTZ Datasheet HTML 3Page - Analog Devices AD7654ASTZ Datasheet HTML 4Page - Analog Devices AD7654ASTZ Datasheet HTML 5Page - Analog Devices AD7654ASTZ Datasheet HTML 6Page - Analog Devices AD7654ASTZ Datasheet HTML 7Page - Analog Devices AD7654ASTZ Datasheet HTML 8Page - Analog Devices AD7654ASTZ Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 28 page
background image
AD7654
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
CONVERSION AND RESET (See Figure 22 and Figure 23)
Convert Pulse Width
t1
5
ns
Time Between Conversions
(Normal Mode/Impulse Mode)
t2
2/2.25
μs
CNVST Low to BUSY High Delay
t3
32
ns
BUSY High All Modes Except in Master Serial Read After Convert Mode
(Normal Mode/Impulse Mode)
t4
1.75/2
μs
Aperture Delay
t5
2
ns
End of Conversions to BUSY Low Delay
t6
10
ns
Conversion Time
(Normal Mode/Impulse Mode)
t7
1.75/2
μs
Acquisition Time
t8
250
ns
RESET Pulse Width
t9
10
ns
CNVST Low to EOC High Delay
t10
30
ns
EOC High for Channel A Conversion
(Normal Mode/Impulse Mode)
t11
1/1.25
μs
EOC Low after Channel A Conversion
t12
45
ns
EOC High for Channel B Conversion
t13
0.75
μs
Channel Selection Setup Time
t14
250
ns
Channel Selection Hold Time
t15
30
ns
PARALLEL INTERFACE MODES (See Figure 24 to Figure 28)
CNVST Low to DATA Valid Delay
t16
1.75/2
μs
DATA Valid to BUSY Low Delay
t17
14
ns
Bus Access Request to DATA Valid
t18
40
ns
Bus Relinquish Time
t19
5
15
ns
A/B Low to Data Valid Delay
t20
40
ns
MASTER SERIAL INTERFACE MODES (see Figure 29 and Figure 30)
CS Low to SYNC Valid Delay
t21
10
ns
CS Low to Internal SCLK Valid Delay1
t22
10
ns
CS Low to SDOUT Delay
t23
10
ns
CNVST Low to SYNC Delay (Read During Convert)
(Normal Mode/Impulse Mode)
t24
250/500
ns
SYNC Asserted to SCLK First Edge Delay
t25
3
ns
Internal SCK Period2
t26
23
40
ns
Internal SCLK High2
t27
12
ns
Internal SCLK Low2
t28
7
ns
SDOUT Valid Setup Time2
t29
4
ns
SDOUT Valid Hold Time2
t30
2
ns
SCLK Last Edge to SYNC Delay2
t31
1
ns
CS High to SYNC HI-Z
t32
10
ns
CS High to Internal SCLK HI-Z
t33
10
ns
CS High to SDOUT HI-Z
t34
10
ns
BUSY High in Master Serial Read After Convert2
t35
See Table 4
CNVST Low to SYNC Asserted Delay
(Normal Mode/Impulse Mode)
t36
0.75/1
μs
SYNC Deasserted to BUSY Low Delay
t37
25
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com