AD7654ASTZ datasheet(22/28 Pages) AD

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AD7654

Rev. B | Page 22 of 28

SLAVE SERIAL INTERFACE

External Clock

The AD7654 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/INT pin is

held high. In this mode, several methods can be used to read

the data. The external serial clock is gated by CS. When both CS

and RD are low, the data can be read after each conversion or

during the following conversion. The external clock can be

either a continuous or discontinuous clock. A discontinuous

clock can be either normally high or normally low when

inactive. Figure 32 and Figure 33 show the detailed timing

diagrams of these methods.

While the AD7654 is performing a bit decision, it is important

that voltage transients not occur on digital input/output pins or

degradation of the conversion result could occur. This is

particularly important during the second half of the conversion

phase of each channel because the AD7654 provides error

correction circuitry that can correct for an improper bit

decision made during the first half of the conversion phase. For

this reason, it is recommended that when an external clock is

provided, it is a discontinuous clock that toggles only when

BUSY is low or, more importantly, that it does not transition

during the latter half of EOC high.

External Discontinuous Clock Data Read After Convert

Although the maximum throughput cannot be achieved in this

mode, it is the most recommended of the serial slave modes.

Figure 32 shows the detailed timing diagrams of this method.

After a conversion is complete, indicated by BUSY returning

low, the conversion results can be read while both CS and RD

are low. Data is shifted out from both channels MSB first, with

32 clock pulses and is valid on both rising and falling edges of

the clock.

One advantage of this method is that conversion performance is

not degraded because there are no voltage transients on the

digital interface during the conversion process. Another

advantage is the ability to read the data at any speed up to 40

MHz, which accommodates both a slow digital host interface

and the fastest serial reading.

Finally, in this mode only, the AD7654 provides a daisy-chain

feature using the RDC/SDIN (serial data in) input pin for

cascading multiple converters together. This feature is useful for

reducing component count and wiring connections when it is

desired, as in isolated multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 31. Simultaneous sampling is possible by using a

common CNVST signal. Note that the RDC/SDIN input is

latched on the edge of SCLK opposite the one used to shift out

the data on SDOUT. Therefore, the MSB of the upstream

converter follows the LSB of the downstream converter on the

next SCLK cycle. The SDIN input should be tied either high or

low on the most upstream converter in the chain.

BUSY

AD7654

#2 (UPSTREAM)

AD7654

#1 (DOWNSTREAM)

RDC/SDIN

SDOUT

CNVST

SCLK

RDC/SDIN

SDOUT

CNVST

SCLK

DATA

OUT

SCLK IN

CS IN

CNVST IN

BUSY

OUT

Figure 31. Two AD7654s in a Daisy-Chain Configuration

External Clock Data Read Previous During Convert

Figure 33 shows the detailed timing diagrams of this method.

During a conversion, while both CS and RD are low, the result

of the previous conversion can be read. The data is shifted out

MSB first with 32 clock pulses and is valid on both the rising

and falling edges of the clock. The 32 bits have to be read before

the current conversion is completed; otherwise, RDERROR is

pulsed high and can be used to interrupt the host interface to

prevent incomplete data reading. There is no daisy-chain

feature in this mode, and RDC/SDIN input should always be

tied either high or low.

To reduce performance degradation due to digital activity, a

fast discontinuous clock (at least 32 MHz in impulse mode and

40 MHz in normal mode) is recommended to ensure that all of

the bits are read during the first half of each conversion phase

(EOC high, t11, t12).

It is also possible to begin to read data after conversion and

continue to read the last bits after a new conversion has been

initiated. This allows the use of a slower clock speed like

26 MHz in impulse mode and 30 MHz in normal mode.

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