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PIC16F1459-ESSQTP 数据表(PDF) 28 Page - Microchip Technology |
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PIC16F1459-ESSQTP 数据表(HTML) 28 Page - Microchip Technology |
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28 / 418 page ![]() PIC16(L)F1454/5/9 DS41639A-page 28 Preliminary 2012 Microchip Technology Inc. 3.3.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appro- priate peripheral chapter of this data sheet. 3.3.2 GENERAL PURPOSE RAM There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 3.3.2.1 Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.6.2 “Linear Data Memory” for more information. Refer to Table 3-3 for Dual Port and USB addressing information. 3.3.3 DUAL-PORT RAM Part of the data memory is mapped to a special dual access RAM. When the USB module is disabled, the GPRs in these banks are used like any other GPR in the data memory space. When the USB module is enabled, the memory in these banks is allocated as buffer RAM for USB operation. This area is shared between the microcontroller core and the USB Serial Interface Engine (SIE) and is used to transfer data directly between the two. It is theoretically possible to use the areas of USB RAM that are not allocated as USB buffers for normal scratchpad memory or other variable storage. In practice, the dynamic nature of buffer allocation makes this risky at best. Additional information on USB RAM and buffer operation is provided in Section 26.0 “Universal Serial Bus (USB)”. 3.3.4 COMMON RAM There are 16 bytes of common RAM accessible from all banks. TABLE 3-3: DUAL PORT RAM ADDRESSING Port 0 Port 1 CPU Banked Address CPU Linear Address USB Banked Address USB Linear Address 020 - 06F 2000 - 204F 020 - 06F 2000 - 204F 0A0 - 0EF 2050 - 209F 0A0 - 0EF 2050 - 209F 120 - 16F 20A0 - 20EF 120 - 16F 20A0 - 20EF 1A0 - 1EF 20F0 - 213F 1A0 - 1EF 20F0 - 213F 220 - 26F 2140 - 218F 220 - 26F 2140 - 218F 2A0 - 2EF 2190 - 21DF 2A0 - 2EF 2190 - 21DF 320 - 32F 21E0 - 21EF 320 - 32F 21E0 - 21EF 370 - 37F (1) 370 - 37F (1) Note 1: Accessible from banked memory only. |
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