PIC16F1459-ESSQTP datasheet(64/418 Pages) MICROCHIP

64 / 418 page

PIC16(L)F1454/5/9

DS41639A-page 64

Preliminary

 2012 Microchip Technology Inc.

5.2.2.5

Internal Oscillator Frequency

Selection Using the PLL

The Internal Oscillator Block can be used with the PLL

associated with the External Oscillator Block to

produce a 24 MHz, 32 MHz or 48 MHz internal system

clock source. The following settings are required to use

the PLL internal clock sources:

• The FOSC bits of the Configuration Words must

be set to use the INTOSC source as the device

system clock (FOSC<2:0> = 100).

• The SCS bits of the OSCCON register must be

cleared to use the clock determined by

FOSC<2:0> in Configuration Words

(SCS<1:0> = 00).

• For 24 MHz or 32 MHz, the IRCF bits of the

OSCCON register must be set to the 8 MHz

HFINTOSC set to use (IRCF<3:0> = 1110).

• For 48 MHz, the IRCF bits of the OSCCON regis-

ter must be set to the 16 MHz HFINTOSC set to

use (IRCF<3:0> = 1111).

• For 24 MHz or 48 MHz, the 3x PLL is required.

The SPLLMULT of the OSCCON register must be

set to use (SPLLMULT = 1).

• For 32 MHz, the 4x PLL is required. The

SPLLMULT of the OSCCON register must be

clear to use (SPLLMULT = 0).

• The SPLLEN bit of the OSCCON register must be

set to enable the PLL, or the PLLEN bit of the

Configuration Words must be programmed to a

'1'.

The PLL is not available for use with the internal oscil-

lator when the SCS bits of the OSCCON register are

set to '1x'. The SCS bits must be set to '00' to use the

PLL with the internal oscillator.

5.2.2.6

Internal Oscillator Clock Switch

Timing

When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut

down to save power (see Figure 5-7). If this is the case,

there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC and

LFINTOSC oscillators. The sequence of a frequency

selection is as follows:

IRCF<3:0> bits of the OSCCON register are

modified.

If the new clock is shut down, a clock start-up

delay is started.

Clock switch circuitry waits for a falling edge of

the current clock.

The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

The new clock is now active.

The OSCSTAT register is updated as required.

Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 5-3.

Start-up delay specifications are located in the

oscillator

tables

Section 29.0

“Electrical

Specifications”.

Note:

When using the PLLEN bit of the

Configuration Words, the PLL cannot be

disabled by software. The 8 MHz and 16

MHz HFINTOSC options will no longer be

available.

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