PIC16F1459-ESSQTP datasheet(68/418 Pages) MICROCHIP

68 / 418 page

PIC16(L)F1454/5/9

DS41639A-page 68

Preliminary

 2012 Microchip Technology Inc.

5.5

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

using the SCS bits:

• Default system oscillator determined by FOSC

bits in Configuration Words

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

5.5.1

SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON

the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the secondary

oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-3.

5.5.2

OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The Oscillator Start-up Timer Status (OSTS) bit of the

OSCSTAT register indicates whether the system clock

is running from the external clock source, as defined by

the FOSC<2:0> bits in the Configuration Words, or

from the internal clock source. In particular, OSTS

indicates that the Oscillator Start-up Timer (OST) has

timed out for LP, XT or HS modes. The OST does not

reflect the status of the secondary oscillator.

5.5.3

SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized

for timekeeping operations with a 32.768 kHz crystal

connected between the SOSCO and SOSCI device

pins.

The secondary oscillator is enabled using the

T1OSCEN control bit in the T1CON register. See

Section 20.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

5.5.4

SECONDARY OSCILLATOR READY

(SOSCR) BIT

The user must ensure that the secondary oscillator is

ready to be used before it is selected as a system clock

source. The Secondary Oscillator Ready (SOSCR) bit

of the OSCSTAT register indicates whether the

secondary oscillator is ready to be used. After the

SOSCR bit is set, the SCS bits can be configured to

select the secondary oscillator.

Note:

Any automatic clock switch, which may

occur

from

Two-Speed

Start-up

Fail-Safe Clock Monitor, does not update

the SCS bits of the OSCCON register. The

user can monitor the OSTS bit of the

OSCSTAT register to determine the current

system clock source.

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