MPC8314VRADDA datasheet(98/101 Pages) FREESCALE

98 / 101 page

MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Ordering Information

This table summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,

nominal NVDD, 105

C.

25.6

Configuration Pin Multiplexing

The MPC8314E provides the user with power-on configuration options that can be set through the use of

external pull-up or pull-down resistors of 4.7 k

 on certain output pins (see customer visible configuration

pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is

disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections

to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should

minimize the disruption of signal quality or speed for output pins thus configured.

25.7

Pull-Up Resistor Requirements

The MPC8314E requires high resistance pull-up resistors (10 k

 is recommended) on open drain type pins

including I2C pins and EPIC interrupt pins.

For more information on required pull up resistors and the connections required for JTAG interface, see

AN3438, MPC8315 Design Checklist

Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 26.1, “Part Numbers Fully Addressed by this Document.”

26.1

Part Numbers Fully Addressed by this Document

This table provides the Freescale part numbering nomenclature for the MPC8314E. Note that the

individual part numbers correspond to a maximum processor core frequency. For available frequencies,

contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme

Table 76. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI Signals

(not including PCI

Output Clocks)

PCI Output Clocks

(including

PCI_SYNC_OUT)

DDR DRAM

Symbol

Unit

42 Target

25 Target

42 Target

20 Target



42 Target

25 Target

42 Target

20 Target



Differential

ZDIFF



Note: Nominal supply voltages. See Table 1, Tj = 105C.

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