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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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3.0-VLVCMOS 数据表(PDF) 19 Page - Altera Corporation |
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3.0-VLVCMOS 数据表(HTML) 19 Page - Altera Corporation |
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19 / 34 page  Chapter 1: Cyclone III Device Datasheet 1–19 Switching Characteristics July 2012 Altera Corporation Cyclone III Device Handbook Volume 2 Device operation in Mbps ×10 100 — 170 100 — 170 100 — 170 Mbps ×8 80 — 170 80 — 170 80 — 170 Mbps ×7 70 — 170 70 — 170 70 — 170 Mbps ×4 40 — 170 40 — 170 40 — 170 Mbps ×2 20 — 170 20 — 170 20 — 170 Mbps ×1 10 — 170 10 — 170 10 — 170 Mbps tDUTY — 45 — 55 45 — 55 45 — 55 % TCCS — — — 200 — — 200 — — 200 ps Output jitter (peak to peak) — — — 500 — — 500 — — 550 ps tRISE 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — ps tFALL 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — ps tLOCK (2) —— — 1 — — 1 — — 1 ms Notes to Table 1–27: (1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks. (2) tLOCK is the time required for the PLL to lock from the end of device configuration. Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 2 of 2) Symbol Modes C6 C7, I7 C8, A7 Unit Min Typ Max Min Typ Max Min Typ Max Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 1 of 2) Symbol Modes C6 C7, I7 C8, A7 Unit Min Typ Max Min Typ Max Min Typ Max fHSCLK (input clock frequency) ×10 5 — 200 5 — 155.5 5 — 155.5 MHz ×8 5 — 200 5 — 155.5 5 — 155.5 MHz ×7 5 — 200 5 — 155.5 5 — 155.5 MHz ×4 5 — 200 5 — 155.5 5 — 155.5 MHz ×2 5 — 200 5 — 155.5 5 — 155.5 MHz ×1 5 — 400 5 — 311 5 — 311 MHz Device operation in Mbps ×10 100 — 400 100 — 311 100 — 311 Mbps ×8 80 — 400 80 — 311 80 — 311 Mbps ×7 70 — 400 70 — 311 70 — 311 Mbps ×4 40 — 400 40 — 311 40 — 311 Mbps ×2 20 — 400 20 — 311 20 — 311 Mbps ×1 10 — 400 10 — 311 10 — 311 Mbps tDUTY — 45 — 55 45 — 55 45 — 55 % TCCS — — — 200 — — 200 — — 200 ps |
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