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3.0-VLVCMOS 数据表(PDF) 20 Page - Altera Corporation |
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3.0-VLVCMOS 数据表(HTML) 20 Page - Altera Corporation |
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20 / 34 page ![]() 1–20 Chapter 1: Cyclone III Device Datasheet Switching Characteristics Cyclone III Device Handbook July 2012 Altera Corporation Volume 2 Output jitter (peak to peak) — — — 500 — — 500 — — 550 ps tRISE 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — ps tFALL 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — ps tLOCK (3) —— — 1 — — 1 — — 1 ms Notes to Table 1–28: (1) Applicable for true and emulated mini-LVDS transmitter. (2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported at the output pin of all I/O banks. (3) tLOCK is the time required for the PLL to lock from the end of device configuration. Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 2 of 2) Symbol Modes C6 C7, I7 C8, A7 Unit Min Typ Max Min Typ Max Min Typ Max |
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