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3.0-VLVCMOS 数据表(PDF) 22 Page - Altera Corporation |
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3.0-VLVCMOS 数据表(HTML) 22 Page - Altera Corporation |
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22 / 34 page  1–22 Chapter 1: Cyclone III Device Datasheet Switching Characteristics Cyclone III Device Handbook July 2012 Altera Corporation Volume 2 External Memory Interface Specifications Cyclone III devices support external memory interfaces up to 200 MHz. The external memory interfaces for Cyclone III devices are auto-calibrating and easy to implement. f For more information about external memory system performance specifications, board design guidelines, timing analysis, simulation, and debugging information, refer to Literature: External Memory Interfaces. Output jitter (peak to peak) — — 500 — 500 — 550 ps tLOCK (2) — — 1—1—1 ms Notes to Table 1–30: (1) Emulated LVDS transmitter is supported at the output pin of all I/O banks. (2) tLOCK is the time required for the PLL to lock from the end of device configuration. Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications (1) Symbol Modes C6 C7, I7 C8, A7 Unit Min Max Min Max Min Max fHSCLK (input clock frequency) ×10 5 437.5 5 370 5 320 MHz ×8 5 437.5 5 370 5 320 MHz ×7 5 437.5 5 370 5 320 MHz ×4 5 437.5 5 370 5 320 MHz ×2 5 437.5 5 370 5 320 MHz ×1 5 437.5 5 402.5 5 402.5 MHz HSIODR ×10 100 875 100 740 100 640 Mbps ×8 80 875 80 740 80 640 Mbps ×7 70 875 70 740 70 640 Mbps ×4 40 875 40 740 40 640 Mbps ×2 20 875 20 740 20 640 Mbps ×1 10 437.5 10 402.5 10 402.5 Mbps SW — — 400 — 400 — 400 ps Input jitter tolerance — — 500 — 500 — 550 ps tLOCK (2) — —1—1— 1 ms Notes to Table 1–31: (1) LVDS receiver is supported at all banks. (2) tLOCK is the time required for the PLL to lock from the end of device configuration. Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 2 of 2) Symbol Modes C6 C7, I7 C8, A7 Unit Min Max Min Max Min Max |
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