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5CSXC4 数据表(PDF) 46 Page - Altera Corporation |
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5CSXC4 数据表(HTML) 46 Page - Altera Corporation |
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46 / 74 page  2–16 Chapter 2: Device Datasheet for Cyclone V Devices Switching Characteristics Cyclone V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet Transmitter Supported I/O Standards 1.5 V PCML Data rate — 614 — 3125 614 — 3125 614 — 2500 Mbps VOCM — — 650 — — 650 — — 650 — mV Differential on-chip termination resistors 85 −Ω setting — 85 — — 85 — — 85 — Ω 100 −Ω setting — 100 — — 100 — — 100 — Ω 120 −Ω setting — 120 — — 120 — — 120 — Ω 150- Ω setting — 150 — — 150 — — 150 — Ω Rise time (6) — 30 — 160 30 — 160 30 — 160 ps Fall time (6) — 30 — 160 30 — 160 30 — 160 ps CMU PLL Supported data range — 614 — 3125 614 — 3125 614 — 2500 Mbps Transceiver-FPGA Fabric Interface Interface speed (single-width mode) — 25 — 187.5 25 — 163.84 25 — 156.25 MHz Interface speed (double-width mode) — 25 — 163.84 25 — 163.84 25 — 156.25 MHz Notes to Table 2–20: (1) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. (2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level. (3) The device cannot tolerate prolonged operation at this absolute maximum. (4) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (5) The rate matcher supports only up to ±300 parts per million (ppm). (6) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 3 of 3) Symbol/ Description Conditions C6 Speed Grade C7, I7 Speed Grade C8, A7 Speed Grade Unit Min Typ Max Min Typ Max Min Typ Max |
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