5CSXC4 datasheet(68/74 Pages) ALTERA

68 / 74 page

2–38

Chapter 2: Device Datasheet for Cyclone V Devices

Glossary

Cyclone V Device Handbook

February 2012

Altera Corporation

Volume 1: Device Overview and Datasheet

High-speed I/O block—Deserialization factor (width of parallel data bus).

JTAG Timing

Specifications

JTAG Timing Specifications:

——

PLL

Specifications

Diagram of PLL Specifications (1)

Note:

(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.

——

Receiver differential input discrete resistor (external to the Cyclone V device).

Table 2–43. Glossary Table (Part 2 of 4)

Letter

Subject

Definitions

TDO

TCK

tJPZX

JPCO

tJPH

t JPXZ

tJCP

tJPSU

t JCL

tJCH

TDI

TMS

Core Clock

External Feedback

Reconfigurable in User Mode

Key

CLK

PFD

Switchover

Delta Sigma

Modulator

VCO

CLKOUT Pins

GCLK

RCLK

fINPFD

fIN

fVCO

fOUT

fOUT_EXT

Counters

C0..C17

5CSXC4 数据表(PDF) 68 Page - Altera Corporation

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