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5CSXC4 数据表(PDF) 11 Page - Altera Corporation |
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5CSXC4 数据表(HTML) 11 Page - Altera Corporation |
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11 / 74 page  Chapter 1: Overview for Cyclone V Device Family 1–5 Cyclone V Family Plan February 2012 Altera Corporation Cyclone V Device Handbook Volume 1: Device Overview and Datasheet Table 1–4 and Table 1–5 list the Cyclone V SE, SX, and ST maximum resource counts. Table 1–4. Maximum Resource Counts for Cyclone V SE Devices—Preliminary Resource Cyclone V SE Devices 5CSEA2 5CSEA4 5CSEA5 5CSEA6 ALM 9,434 15,094 32,075 41,509 LE 25,000 40,000 85,000 110,000 Block Memory (Kb) 1,400 2,240 3,972 5,140 MLAB Memory (Kb) 138 220 480 621 Variable-precision DSP Block 36 58 87 112 18 x 19 Multiplier 72 116 174 224 FPGA Fractional PLL 4 5 6 6 HPS PLL 3 3 3 3 FPGA GPIO 124 124 288 288 HPS I/O 188 188 188 188 LVDS 31 31 72 72 FPGA Memory Controller — 1 1 1 HPS Memory Controller 1 1 1 1 ARM Cortex-A9 MPCore Processor Single- or dual-core Single- or dual-core Single- or dual-core Single- or dual-core Table 1–5. Maximum Resource Counts for Cyclone V SX and ST Devices—Preliminary (Part 1 of 2) Resource Cyclone V SX Device Cyclone V ST Device 5CSXC4 5CSXC5 5CSXC6 5CSTD5 5CSTD6 ALM 15,094 32,075 41,509 32,075 41,509 LE 40,000 85,000 110,000 85,000 110,000 Block Memory (Kb) 2,240 3,972 5,140 3,972 5,140 MLAB Memory (Kb) 220 480 621 480 621 Variable-precision DSP Block 58 87 112 87 112 18 x 19 Multiplier 116 174 224 174 224 FPGA Fractional PLL (1) 56 666 HPS PLL 3 3 3 3 3 3-Gbps Transceiver 6 9 9 — — 5-Gbps Transceiver — — — 9 9 FPGA GPIO 124 288 288 288 288 HPS I/O 188 188 188 188 188 LVDS 31 72 72 72 72 |
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