5CSXC4 datasheet(9/74 Pages) ALTERA

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Chapter 1: Overview for Cyclone V Device Family

1–3

Cyclone V Features Summary

February 2012

Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

HPS

(Cyclone V SE, SX,

and ST devices

only)

■ Dual-core ARM Cortex-A9 MPCore processor—up to 800 MHz maximum frequency with support

for symmetric and asymmetric multiprocessing

■ Interface peripherals—10/100/1000 Ethernet media access control (MAC), USB 2.0 On-The-GO

(OTG) controller, serial peripheral interface (SPI), Quad SPI flash controller, NAND flash controller,

SD/MMC/SDIO controller, UART, controller area network (CAN), I2C interface, and up to 71 HPS I/O

interfaces

■ System peripherals—general-purpose and watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

■ On-chip RAM and boot ROM

■ HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to master transactions to slaves in the HPS, and vice versa.

■ FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

■ ARM CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

High-performance

FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory

blocks

■ M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

■ Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of

the ALMs as MLAB memory

Phase-locked

loops (PLLs)

■ Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

■ Integer mode and fractional mode

Clock networks

■ 550 MHz global clock network

■ Global, quadrant, and peripheral clock networks

■ Clock networks that are not used can be powered down to reduce dynamic power

Configuration

■ Partial and dynamic reconfiguration of the FPGA

■ CvP

■ Active serial (AS) x1 and x4, fast passive parallel (FPP) x8 and x16, passive serial (PS), and JTAG

options

■ Enhanced advanced encryption standard (AES) design security features

■ Tamper protection

Packaging

■ Wirebond low-halogen packages

■ Multiple device densities with compatible package footprints for seamless migration between

different device densities

■ RoHS-compliant options

Table 1–1. Summary of Features for Cyclone V Devices (Part 2 of 2)

Feature

Details

5CSXC4 数据表(PDF) 9 Page - Altera Corporation

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