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Chapter 2: Device Datasheet for Cyclone V Devices

Configuration Specification

Cyclone V Device Handbook

February 2012

Altera Corporation

Volume 1: Device Overview and Datasheet

Configuration Specification

This section provides configuration specifications and timing for Cyclone V devices.

These characteristics can be designated as preliminary or final.

■

Preliminary characteristics are obtained using simulation results, process data,

and other known parameters. The title of these tables show the designation as

“Preliminary.”

■

Final numbers are based on actual silicon characterization and testing. The

numbers reflect the actual performance of the device under worst-case silicon

process, voltage, and junction temperature conditions. There are no designations

on finalized tables.

POR Specifications

Table 2–31 lists the specifications for fast and standard POR delay for Cyclone V

devices.

JTAG Configuration Timing

Table 2–32 lists the JTAG timing parameters and values for Cyclone V devices.

Table 2–31. Fast and Standard POR Delay Specification for Cyclone V Devices

POR Delay

PORSEL Pin Setting

Minimum (ms)

Maximum (ms)

Fast (1)

High

Standard

GND

100

300

Note to Table 2–31:

(1) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize

after the POR trip.

Table 2–32. JTAG Timing Parameters and Values for Cyclone V Devices—Preliminary

Symbol

Description

Min

Max

Unit

tJCP

TCK clock period

—

tJCH

TCK clock high time

—

tJCL

TCK clock low time

—

tJPSU (TDI)

TDI JTAG port setup time

—

tJPSU (TMS)

TMS JTAG port setup time

—

tJPH

JTAG port hold time

—

tJPCO

JTAG port clock to output

—

11 (1)

tJPZX

JTAG port high impedance to valid output

—

14 (1)

tJPXZ

JTAG port valid output to high impedance

—

14 (1)

Note to Table 2–32:

(1) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO

I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.

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