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TLP708 数据表(PDF) 4 Page - Toshiba Semiconductor |
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TLP708 数据表(HTML) 4 Page - Toshiba Semiconductor |
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4 / 13 page ![]() TLP708,TLP708F 2012-08-07 4 Switching Characteristics (Unless otherwise specified, Ta = -40 to 125°C, VCC = 4.5 to 5.5 V) Characteristic Symbol Test Circuit Test Conditions Min. Typ.* Max. Unit Propagation delay time to logic low output tpHL IF=0→7.5mA — 35 75 ns Propagation delay time to logic high output tpLH IF=7.5→0mA RL=350Ω CL=15pF (Note 4) — 35 75 ns Switching time dispersion between ON and OFF |tpHL- tpLH| — 12 35 ns Propagation delay skew (Note 5) tpsk IF=0↔7.5mA RL=350Ω CL=15pF (Note 4) -50 — 50 ns Output fall time(90-10%) tf IF=0→7.5mA — 6 — ns Output rise time(10-90%) tr 5 IF=7.5→0mA RL =350Ω CL=15pF (Note 4) — 18 — ns Common mode transient immunity at high level output CMH VCM=1000Vp-p , IF=0mA, VCC=5V , Ta=25℃ + 15 — — kV/μs Common mode transient immunity at low level output CML 6 VCM=1000Vp-p , IF=10mA, VCC=5V , Ta=25℃ - 15 — — kV/μs *All typical values are at Ta=25 ℃ Note 3 : A ceramic capacitor (0.1 μF) should be connected from pin 6 (VCC) to pin 4 (GND) to stabilize the operation of the high gain linear amplifier. Failure to provide the bypass may impair the switching property. The total lead length between the capacitor and coupler should not exceed 1 cm. Note 4 : f=5MHz, duty=50%, input current tr=tf=4.5ns, CL is approximately 15pF which includes probe and jig/stray wiring capacitance. Note 5: Propagation delay skew is defined as the difference between the largest and smallest propagation delay times (i.e. tpHL or tpLH) of multiple samples. Evaluations of these samples are conducted under identical test conditions (supply voltage, input current, temperature, etc). TEST CIRCUIT 1: IOH Test Circuit TEST CIRCUIT 2: VOL Test Circuit TEST CIRCUIT 3: ICCL Test Circuit TEST CIRCUIT 4: ICCH Test Circuit A VCC 0.1 μF ICCH SHIELD 1 2 3 6 5 4 IF A VCC 0.1 μF ICCL SHIELD 1 2 3 6 5 4 0.1μF VOL VCC V IO ↑ IF SHIELD 1 2 3 6 5 4 0.1μF SHIELD VF VCC IOH A VO 1 2 3 6 5 4 |
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