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INA226AIDGST 数据表(PDF) 5 Page - Texas Instruments |
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INA226AIDGST 数据表(HTML) 5 Page - Texas Instruments |
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5 / 33 page ![]() GND V S+ V BUS SCL 1 2 3 4 5 10 9 8 7 6 A1 A0 SDA Alert VIN+ VIN - ADC ´ ´ Shunt Voltage Channel Bus Voltage Channel Shunt Voltage (1) Data Registers Calibration (2) Current (1) Bus Voltage (1) Power (1) INA226 www.ti.com SBOS547 – JUNE 2011 PIN CONFIGURATIONS DGS PACKAGE MSOP-10 (Top View) PIN DESCRIPTIONS MSOP-10 (DGS) PIN NO NAME DESCRIPTION 1 A1 Address pin. Connect to GND, SCL, SDA, or VS. Table 7 shows pin settings and corresponding addresses. 2 A0 Address pin. Connect to GND, SCL, SDA, or VS. Table 7 shows pin settings and corresponding addresses. 3 Alert Multi-functional alert, open-drain output. 4 SDA Serial bus data line, open-drain input/output. 5 SCL Serial bus clock line, open-drain input. 6 VS+ Power supply, 2.7V to 5.5V. 7 GND Ground. 8 VBUS Bus voltage input. 9 VIN – Negative differential shunt voltage. Connect to negative side of shunt resistor. 10 VIN+ Positive differential shunt voltage. Connect to positive side of shunt resistor. REGISTER BLOCK DIAGRAM (1) Read-only (2) Read/write Figure 1. INA226 Register Block Diagram Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): INA226 |
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