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INA226AIDGST 数据表(PDF) 13 Page - Texas Instruments |
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INA226AIDGST 数据表(HTML) 13 Page - Texas Instruments |
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13 / 33 page ![]() INA226 www.ti.com SBOS547 – JUNE 2011 ALERT PIN The INA226 has a single Alert Limit register, 07h, that allows the Alert pin to be programmed to respond to a single user-defined event or to a conversion ready notification if desired. The Mask/Enable Register allows the user to select from one of the five available functions to monitor and/or set the conversion ready bit to control the response of the Alert pin. Based on the function being monitored, the user would then enter a value into the Alert Limit Register to set the corresponding threshold value that asserts the Alert pin. The Alert pin allows for one of several available alert functions to be monitored to determine if a user-defined threshold has been exceeded. The five alert functions that can be monitored are: • Shunt Voltage Over Limit (SOL) • Shunt Voltage Under Limit (SUL) • Bus Voltage Over Limit (BOL) • Bus Voltage Under Limit (BUL) • Power Over Limit (POL) The Alert pin is an open-drain output. This pin is asserted when the alert function selected in the Mask/Enable register exceeds the value programmed into the Alert Limit register. Only one of these alert functions can be enabled and monitored at a time. If multiple alert functions are enabled, the selected function in the highest significant bit position takes priority and responds to the Alert Limit register value. For example, if the Shunt Voltage Over Limit and the Shunt Voltage Under Limit are both selected, the Alert pin asserts when the Shunt Voltage Over Limit Register exceeds the value in the Alert Limit register. The Conversion Ready state of the device can also be monitored at the Alert pin to inform the user when the device has completed the previous conversion and is ready to begin a new conversion. Conversion Ready can be monitored at the Alert pin along with one of the alert functions. If an alert function and the Conversion Ready are both enabled to be monitored at the Alert pin, after the Alert pin is asserted, the Mask/Enable register must be read following the alert to determine the source of the alert. By reading the Conversion Ready Flag (CVRF), bit D3, and the Alert Function Flag (AFF), bit D4 in the Mask/Enable register, the source of the alert can be determined. If the conversion ready feature is not desired, and the CNVR bit is not set, the Alert pin only responds to an exceeded alert limit based on the alert function enabled. If the Alert function is not used, the Alert pin can be left floating without impacting the operation of the device. Refer to Figure 20 to see the relative timing of when the value in the Alert Limit Register is compared to the corresponding converted value. For example, if the alert function that is enabled is Shunt Voltage Over Limit (SOL), following every shunt voltage conversion the value in the Alert Limit Register is compared to the measured shunt voltage to determine if the measurements has exceeded the programmed limit. The AFF, bit 4 of the Mask/Enable Register, asserts high any time the measured voltage exceeds the value programmed into the Alert Limit Register. In addition to the AFF being asserted, the Alert pin is asserted based on the Alert Polarity Bit (APOL, bit 1 of the Mask/Enable Register). If the Alert Latch is enabled, the AFF and Alert pin remain asserted until either the Configuration Register is written to or the Mask/Enable Register is read. The Bus Voltage alert functions compare the measured bus voltage to the Alert Limit Register following every bus voltage conversion and assert the AFF bit and Alert pins if the limit threshold is exceeded. The Power Over Limit alert function is also compared to the calculated power value following every bus voltage measurement conversion and asserts the AFF bit and Alert pins if the limit threshold is exceeded. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): INA226 |
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