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INA226AIDGST 数据表(PDF) 21 Page - Texas Instruments |
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INA226AIDGST 数据表(HTML) 21 Page - Texas Instruments |
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21 / 33 page ![]() INA226 www.ti.com SBOS547 – JUNE 2011 Current Register 04h (Read-Only) If averaging is enabled, this register displays the averaged value. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT CSIGN CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE The value of the Current Register is calculated by multiplying the decimal value in the Shunt Voltage Register with the decimal value of the Calibration Register, according to Equation 3. Calibration Register 05h (Read/Write) This register provides the INA226 with the value of the shunt resistor that was present to create the measured differential voltage. It also sets the resolution of the Current Register. The current LSB and power LSB are set through the programming of this register. This register is also suitable for use in overall system calibration. See the Configure/Measure/Calculate Example for additional information on programming the Calibration Register. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT — FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE Mask/Enable 06h (Read/Write) The Mask/Enable Register selects the function that is enabled to control the Alert pin, as well as how that pin functions. If multiple functions are enabled, the highest significant bit position Alert Function (D11-D15) takes priority and responds to the Alert Limit register. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT SOL SUL BOL BUL POL CNVR — — — — — AFF CVRF OVF APOL LEN NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE SOL: Shunt Voltage Over-Voltage Bit 15 Setting this bit high configures the Alert pin to be asserted when the Shunt Voltage Register exceeds the value in the Alert Limit Register. SUL: Shunt Voltage Under-Voltage Bit 14 Setting this bit high configures the Alert pin to be asserted when the Shunt Voltage Register drops below the value in the Alert Limit Register. BOL: Bus Voltage Over-Voltage Bit 13 Setting this bit high configures the Alert pin to be asserted when the Bus Voltage Register exceeds the value in the Alert Limit Register. BUL: Bus Voltage Under-Voltage Bit 12 Setting this bit high configures the Alert pin to be asserted when the Bus Voltage Register drops below the value in the Alert Limit Register. POL: Over-Limit Power Bit 11 Setting this bit high configures the Alert pin to be asserted when the Power Register exceeds the value in the Alert Limit Register. CNVR: Conversion Ready Bit 10 Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready for the next conversion. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link(s): INA226 |
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