Data Sheet

ADP2323

Rev. A | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1SW1

2

BST1

3

DL1

4

PGND

5

VDRV

6

DL2

7

BST2

8

SW2

24

23

22

21

20

19

18

17

PGOOD1

NOTES

1. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GND PLANE.

SCFG

SYNC

GND

INTVCC

RT

MODE

PGOOD2

TOP VIEW

(Not to Scale)

ADP2323

Figure 4. Pin Configuration (Top View)

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

PGOOD1

Power-Good Output (Open Drain) for Channel 1. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.

2

SCFG

Synchronization Configuration Input. The SCFG pin configures the SYNC pin as an input or output. Connect

SCFG to INTVCC to configure SYNC as an output. Using a resistor to pull down to GND configures SYNC as an

input with various phase shift degrees.

3

SYNC

Synchronization. This pin can be configured as an input or an output. When configured as an output, it

provides a clock at the switching frequency. When configured as an input, this pin accepts an external clock

to which the regulators are synchronized and the phase shift is configured by SCFG. Note that when SYNC is

configured as an input, the PFM mode is disabled and the device works only in continuous conduction mode

(CCM).

4

GND

Analog Ground. Connect to the ground plane.

5

INTVCC

Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 μF ceramic

capacitor between INTVCC and GND.

6

RT

Connect a resistor between RT and GND to program the switching frequency between 250 kHz and 1.2 MHz.

7

MODE

Mode Selection. When this pin is connected to INTVCC, the PFM mode is disabled and the regulator works

only in CCM. When this pin is connected to ground, the PFM mode is enabled. If the low-side device is a

diode, the MODE pin must be connected to ground.

8

PGOOD2

Power-Good Output (Open Drain) for Channel 2. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.

9

FB2

Feedback Voltage Sense Input for Channel 2. Connect to a resistor divider from the Channel 2 output voltage,

10

COMP2

Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to GND. Connect COMP1 and

COMP2 together for parallel applications.

11

SS2

Soft Start Control for Channel 2. Connect a capacitor from SS2 to GND to program the soft start time. For

parallel applications, SS2 remains open.

12

TRK2

Tracking Input for Channel 2. To track a master voltage, drive this pin from a voltage divider from the master

voltage. If the tracking function is not used, connect TRK2 to INTVCC.

13

EN2

Enable Pin for Channel 2. An external resistor divider can be used to set the turn-on threshold. When not

using the enable pin, connect EN2 to PVIN2.

14, 15

PVIN2

Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor

between PVIN2 and ground.

16, 17

SW2

Switch Node for Channel 2.

18

BST2

Supply Rail for the Gate Drive of Channel 2. Place a 0.1 μF capacitor between SW2 and BST2.

19

DL2

Low-Side Gate Driver Output for Channel 2. Connect a resistor between DL2 and PGND to program the

current-limit threshold of Channel 2.

20

VDRV

Low-Side Driver Supply Input. Connect VDRV to INTVCC. Place a 1 μF ceramic capacitor between the VDRV

pin and PGND.

21

PGND

Driver Power Ground. Connect to the source of the synchronous N-channel MOSFET.

22

DL1

Low-Side Gate Driver Output for Channel 1. Connect a resistor between this pin and PGND to program the

current-limit threshold of Channel 1.