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ADP2323ACPZ-R7 数据表(PDF) 24 Page - Analog Devices

部件名 ADP2323ACPZ-R7
功能描述  Dual 3 A, 20 V Synchronous Step-Down Regulator with Integrated High-Side MOSFET
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2323ACPZ-R7 数据表(HTML) 24 Page - Analog Devices

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ADP2323
Data Sheet
Rev. A | Page 24 of 32
For the 1.2 V rail, the output capacitor ESR needs to be smaller
than 12 mΩ, and the output capacitance needs to be larger than
191 µF. It is recommend that three pieces of 100 µF/X5R/6.3 V
ceramic capacitor be used, such as the GRM32ER60J107ME20
from Murata, with an ESR = 2 mΩ.
For the 3.3 V rail, the ESR of the output capacitor must be
smaller than 32 mΩ and the output capacitance must be larger
than 54 µF. It is recommended that two pieces of 47 µF/X5R/6.3
V ceramic capacitor be used, such as the Murata
GRM32ER60J476ME20, with an ESR = 2 mΩ.
LOW-SIDE MOSFET SELECTION
A low RDSON N-channel MOSFET is selected for high efficiency
solutions. The MOSFET breakdown voltage needs to be greater
than 1.2 V × VIN, and the drain current needs to be greater than
1.2 V × ILIMIT.
It is recommended that a 30 V, N-channel MOSFET be used, such as
the FDS8880 from Fairchild. The RDSON of the FDS8880 at a 4.5 V
driver voltage is 12 mΩ, and the total gate charge is 12 nC.
COMPENSATION COMPONENTS
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this case, fSW is running at 500 kHz;
therefore, the fC is set to 50 kHz.
For the 1.2 V rail, the 100 µF ceramic output capacitor has
a derated value of 64 µF.
4
.
80
A/V
5
μs
300
V
6
.
0
kHz
50
μF
64
3
V
2
.
1
2
=
×
×
×
×
×
×
π
×
=
C1
R
(
)
pF
957
4
.
80
μF
64
3
Ω
001
.
0
Ω
4
.
0
=
×
×
+
=
1
C
C
pF
4
.
2
4
.
80
μF
64
3
Ω
001
.
0
=
×
×
=
CP1
C
Choose standard components, RC1 = 82 kΩ and CC1 = 1000 pF. No
CCP1 is needed.
Figure 48 shows the 1.2 V rail bode plot at 3 A. The cross
frequency is 49 kHz and the phase margin is 59°.
–60
–48
–36
–24
–12
0
12
24
36
48
60
–180
–144
–108
–72
–36
0
36
72
108
144
180
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 48. Bode Plot for 1.2 V Rail
For the 3.3 V rail, the 47µF ceramic output capacitor has a
derated value of 32 µF.
7
.
73
A/V
5
μs
300
V
6
.
0
kHz
50
μF
32
2
V
3
.
3
2
=
×
×
×
×
×
×
π
×
=
C2
R
(
)
pF
956
7
.
73
μF
32
2
Ω
001
.
0
Ω
1
.
1
=
×
×
+
=
2
C
C
pF
1
7
.
73
μF
32
2
Ω
001
.
0
=
×
×
=
CP2
C
Choose standard component values of RC2 = 75 kΩ and
CC2 = 1000 pF. No CCP2 is needed.
Figure 49 shows the 3.3 V rail bode plot at 3 A. The cross
frequency is 59 kHz and phase margin is 61°.
–60
–48
–36
–24
–12
0
12
24
36
48
60
–180
–144
–108
–72
–36
0
36
72
108
144
180
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 49. Bode Plot for 3.3 V Rail
SOFT START TIME PROGRAMMING
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting inrush current. The soft start time is set
to 3 ms.
nF
5
.
17
V
6
.
0
ms
3
μA
5
.
3
V
6
.
0
=
×
=
×
=
SS
SS
SS
T
I
C
Choose a standard component value of CSS1 = CSS2 = 22 nF.
INPUT CAPACITOR SELECTION
A minimum 10 µF ceramic capacitor is required, placed near
the PVINx pin. In this application, one piece of 10 µF, X5R, 25
V ceramic capacitor is recommended.



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