ADP2323ACPZ-R7 datasheet(16/32 Pages) AD

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ADP2323

Data Sheet

Rev. A | Page 16 of 32

BOOTSTRAP CIRCUITRY

The ADP2323 integrates the boot regulators to provide the gate

drive voltage for the high-side NFETs. The regulators generate 5

V bootstrap voltages between the BSTx pin and the SWx pin.

It is recommended that an X7R or an X5R, 0.1 µF ceramic

capacitor be placed between the BSTx and the SWx pins.

LOW-SIDE DRIVER

The DLx pin provides the gate drive for the low-side N-channel

MOSFET. Internal circuitry monitors the gate driver signal to

ensure break-before-make switching to prevent cross

conduction.

The VDRV pin provides the power supply to the low-side

drivers. It is limited to a 5.5 V maximum input, and placing

a 1 µF ceramic capacitor close to this pin is recommended.

OSCILLATOR

A resistor from RT to GND programs the switching frequency

according to the following equation:

fSW [kHz] =

]

kΩ

[

000

OSC

A 200 kΩ resistor sets the frequency to 300 kHz, and a 100 kΩ

resistor sets the frequency to 600 kHz. Figure 42 shows the

typical relationship between fSW and ROSC.

200

300

400

600

800

500

700

900

1000

1100

1200

130

170

210

110

150

190

230

250

ROSC (kΩ)

Figure 42. fSW vs. ROSC

SYNCHRONIZATION

The SYNC pin can be configured as an input or an output by

setting the SCFG pin as shown in Table 5.

Table 5. SCFG Configuration

SCFG

SYNC

Phase Shift

High

Output

0°

GND

Input

90°

180 kΩ to GND

Input

120°

100 kΩ to GND

Input

60°

When the SYNC pin is configured as an output, it generates a

clock with a frequency that is equal to the internal switching

frequency.

When the SYNC pin is configured as an input, the ADP2323

synchronizes to the external clock that is applied to the SYNC pin,

and the internal clock must be programmed lower than the

external clock. The phase shift can be programmed by the SCFG

pin.

When working in synchronization mode, the ADP2323 disables

the PFM mode and works only in the CCM mode.

SOFT START

The SSx pins are used to program the soft start time. Place a

capacitor between SSx and GND; an internal current charges

this capacitor to establish the soft start ramp. The soft start time

can be calculated using the following equation:

= 6

where:

CSS is the soft start capacitance.

ISS is the soft start pull-up current (3.5 µA).

If the output voltage is precharged prior to power up, the

ADP2323 prevents the low-side MOSFET from turning on until

the soft start voltage exceeds the voltage on the FBx pin.

During soft start, the ADP2323 uses frequency foldback to

prevent output current runaway. The switching frequency is

reduced according to the voltage present at the FBx pin, which

allows more time for the inductor to discharge. The correlation

between the switching frequency and the FBx pin voltage is listed

in Table 6.

Table 6. FBx Pin Voltage and Switching Frequency

FBx Pin Voltage

Switching Frequency

FB ≥ 0.4 V

0.4 V > V

FB ≥ 0.2 V

1/2 f

FB < 0.2 V

1/4 f

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP2323 uses a peak current-limit protection circuit to

prevent current runaway. Place a resistor between DLx and

PGND to program the current-limit value listed in Table 7. The

programmable current-limit threshold feature allows for the use

of a small size inductor for low current applications.

Table 7. Peak Current-Limit Threshold Setting

ILIM

Peak Current-Limit Threshold

Floating

4.8 A

47 kΩ

3 A

15 kΩ

1.5 A

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