ADP2323ACPZ-R7 datasheet(15/32 Pages) AD

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Data Sheet

ADP2323

Rev. A | Page 15 of 32

THEORY OF OPERATION

The ADP2323 is a full featured, dual output, step-down dc-to-

dc regulator based on current-mode architecture. It integrates two

high-side power MOSFETs and two low-side drivers for

external MOSFETs. The ADP2323 targets high performance

applications that require high efficiency and design flexibility.

The ADP2323 can operate with an input voltage from 4.5 V to

20 V, and can regulate the output voltage down to 0.6 V.

Additional features for flexible design include programmable

switching frequency, programmable soft start, external compen-

sation, independent enable inputs, and power good outputs.

CONTROL SCHEME

The ADP2323 uses a fixed frequency, current-mode PWM

control architecture during medium to full loads, but shifts to a

power save mode (PFM) at light loads when the PFM mode is

enabled. The power save mode reduces switching losses and

boosts efficiency under light loads. When operating in the fixed

frequency PWM mode, the duty cycle of the integrated N-

channel MOSFET (referred to interchangeably as NFET or

MOSFET) is adjusted, which, in turn, regulates the output

voltage. When operating in power save mode, the switching

frequency is adjusted to regulate the output voltage.

PWM MODE

In PWM mode, the ADP2323 operates at a fixed frequency that

is set by an external resistor. At the start of each oscillator cycle, the

high-side NFET turns on, placing a positive voltage across the

inductor. The inductor current increases until the current sense

signal crosses the peak inductor current threshold that turns off

the high-side NFET and turns on the low-side NFET (diode). This

places a negative voltage across the inductor causing the

inductor current to reduce. The low-side NFET (diode) stays on

for the remainder of the cycle or until the inductor current reaches

zero.

PFM MODE

Pull the MODE pin to ground to enable the PFM mode. When

the COMPx voltage is below the PFM threshold voltage, the

device enters the PFM mode.

When the device enters the PFM mode, it monitors the FBx

voltage to regulate the output voltage. Because the high-side and

low-side NFETs are turned off, the output voltage drops due to

the load current discharging the output capacitor. When the FBx

voltage drops below 0.605 V, the device starts switching and the

output voltage increases as the output capacitor is charged by the

inductor current. When the FBx voltage exceeds 0.62 V, the device

turns off both the high-side and low-side NFETs until the FBx

voltage drops to 0.605 V. In the PFM mode, the output voltage

ripple is larger than the ripple in the PWM mode.

PRECISION ENABLE/SHUTDOWN

The ADP2323 has two independent enable pins (EN1 and EN2)

for each channel. The ENx pin has an internal pull-down

current source (5 µA) that provides default turn off when an

ENx pin is open.

When the voltage on the EN1 or EN2 pin exceeds 1.2 V

(typical), Channel 1 or Channel 2 is enabled and the internal

pull-down current source at the EN1 or EN2 pin is reduced to 1

µA, which allows the user to program the input voltage

undervoltage lockout (UVLO).

When the voltage on the EN1 or EN2 pin drops below 1.1 V

(typical), Channel 1 or Channel 2 turns off. When EN1 and

EN2 are both below 1.1 V, all of the internal circuits turn off

and the device enters the shutdown mode.

SEPARATE INPUT VOLTAGES

The ADP2323 supports two separate input voltages. This means

that the PVIN1 and PVIN2 voltages can be connected to two

different supply voltages. In these types of applications, the

PVIN1 voltage needs to be above the UVLO voltage before the

PVIN2 voltage begins to rise because the PVIN1voltage provides

the power supply for the internal regulator and control circuitry.

This feature makes it possible for a cascading supply operation as

shown in Figure 41, where PVIN2 is sourced from the Channel 1

output. In this configuration, the Channel 1 output voltage needs

to be high enough to maintain Channel 2 in regulation, and the

Channel 1 output voltage needs to be higher than the input

voltage UVLO threshold.

SW2

DL2

PVIN2

SW1

DL1

PGND

COUT1

PVIN1

ADP2323

VIN

VOUT1

VOUT2

COUT2

Figure 41. Cascading Supply Operation

INTERNAL REGULATOR (INTVCC)

The internal regulator provides a stable voltage supply for the

internal control circuits and bias voltage for the low-side gate

drivers. A 1 µF ceramic capacitor is recommended to be placed

between INTVCC and GND. The internal regulator also

includes a current-limit circuit for protection.

The internal regulator is active when either one of the channels is

enabled. The PVIN1 pin provides power for the internal

regulator that is used by both channels.

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