AM8530 datasheet(27/194 Pages) AMD

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System Interface

AMD

2–9

Table 2–3. Enhancement Options

WR15 bit D2

WR15 D0

WR7

′ bit D6

10x19-bit

SDLC/HDLC

Extended

FIFO Enabled Enhance Enabled

Read Enable

Functions Enabled

10x19-bit FIFO enhancement

enabled only

SDLC/HDLC enhancements

enabled only

SDLC/HDLC enhancements

enabled with extended read

enabled

10x19-bit FIFO and SDLC/

HDLC enhancements enabled

10x19-bit FIFO and SDLC/

HDLC enhancements with

extended read enabled

Bit D0 of WR15 determines whether or not other enhancements pertinent only to SDLC/

HDLC Mode operation are available for programming via WR7

′ as shown below. Write

′ ) can be written to when bit D0 of WR15 is set to ‘1’. When this

bit is set, writing to WR7 (flag register) actually writes to WR7

′. If bit D6 of this register is

set to ‘1’, previously unreadable registers WR3, WR4, WR5, WR10 are readable by the

processor. In addition, WR7

′ is also readable by having this bit set. WR3 is read when a

bogus RR9 register is accessed during a read cycle, WR10 is read by accessing RR11,

and WR7

′ is accessed by executing a read to RR14. The Am85C30 register map with bit

D0 of WR15 and bit D6 of WR7

′ set is shown in Table 2–5.

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