AM8530 datasheet(60/194 Pages) AMD

60 / 194 page

Data Communication Modes Functional Description

AMD

4–8

D4 D3

D2 D1

Figure 4–6. Five Bits/Character with Parity

The character length may be changed at any time before the new number of bits have

been assembled by the receiver. Care should be exercised, however, as unexpected re-

sults may occur if not properly timed. A representative example of switching from five bits

to eight bits and back to five bits is shown in Figure 4–7.

5 BITS

8 BITS

5 BITS

RECEIVE DATA BUFFER

Time

Change From Five to Eight

Change From Eight to Five

Figure 4–7. Changing Character Length

4.4.2

Rx Parity

In all modes of operation bit D0 (Parity Enable) of WR4 determines whether a Parity

check is done. If this bit is set to ‘1’, the receiver calculates a parity check on every char-

acter received, as selected by bit D1 (Parity Even/Odd) of WR4, and compares it with

parity check bit transmitted. If a discrepancy is found the Parity Error status bit in the Re-

ceive Error FIFO is set at the same time that the character is transferred to the Receive

Data FIFO; otherwise, the character received will be assumed to be error free.

The additional bit per character will be visible in the Receive Data FIFO if the data plus

parity is eight bits or less. The parity bit will not be visible when there are eight data bits

per character.

AM8530 数据表(PDF) 60 Page - Advanced Micro Devices