AM8530 datasheet(99/194 Pages) AMD

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Support Circuitry Programming

AMD

5–5

Figure 5–1 shows a simplified schematic diagram of the circuitry used in the clock multi-

plexing. It shows the inputs to the multiplexer section as well as the various signal inver-

sions that occur in the paths to the outputs. Also shown are the edges used by the re-

ceiver, transmitter, BRG, and DPLL to sample or send data or otherwise change state.

For example, the receiver samples data on the falling edge, but since there is an inver-

sion in the clock path between the

RTxC pin and the receiver, a rising edge of the RTxC

pin samples the data for the receiver.

5.2.4

Clock Programming

Selection of the clock options may be done anywhere in the initialization sequence, but

the final values must be selected before the receiver, transmitter, BRG, or DPLL are en-

abled to prevent problems from arbitrarily narrow clock signals out of the multiplexers.

The same is true of the crystal oscillator, in that the output should be allowed to stabilize

before it is used as a clock source.

SYNC

OSC

RTxC

DPLL

Receiver

Transmitter

TRxC

BRG

ECHO

DPLL

Baud Rate

Generator Out

TX DPLL Out

RX DPLL Out

PCLK

Generator

Figure 5–1. Clock Multiplexer

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