AM8530 datasheet(59/194 Pages) AMD

59 / 194 page

Data Communication Modes Functional Description

AMD

4–7

ter with the Special Condition is read from the Data FIFO. Because under these condi-

tions the FIFO is locked, and prevented from being updated, the status pertinent to the

character read will be valid until an Error Reset command is issued via WR0.

4.4.1

Rx Character Length

The number of consecutive bits assembled in the Receive Shift Register that form a char-

acter in all modes of operation is controlled by bits D7 and D6 of WR3. Five, six, seven,

or eight bits per character may be selected via these two bits. The data plus parity bit (if

enabled) received are right-justified in the receive buffer as shown in Figure 4–6. The

SCC merely takes a snapshot of the receive data stream at the appropriate times, so the

“unused” bits in the receive buffer are only the bits following the character in the data

stream.

Upper Byte

Time Constant

Lower Byte

Time Constant

16-Bit Down Counter

BR Generator

Input

10 x 19-Bit

Frame

Status

FIFO

Receive

Data

FIFO

Receive

Error

FIFO

BR Generator

Output

Receive

Error Logic

Receive

Shift Register

(8 Bits)

14-Bit Counter

3 Bits

Sync Register

& Zero Delete

Hunt Mode (Disync)

CRC Delay

(8 Bits)

CRC Checker

CRC Result

Sync-

CRC

SDLC-CRC

MUX

NRZI Decode

Internal

TxD

MUX

1 Bit

RxD

DPLL

DPLL Output

I/O Data Buffer

CPU I/O

Internal Data Bus

Transmi

Section

Figure 4–5. SCC Receiver

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