AM8530 datasheet(62/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–10

WR7 Sync

WR6 Sync

Transmit Data

20-Bit Transmit

Shift Register

Start Bit

Transmit MUX

& 2-Bit Delay

Zero Insert

(5 Bits)

CRC

Generator

NRZI

Encode

Final

Tx MUX

TxD

Internal TxD

Transmit

Clock

To Other Channel

ASYNC

SYNC

SDLC

CRC-SDLC

Internal Data Bus

Figure 4–8. SCC Transmitter

Table 4–1. Data Format—Five Bits or Less

Bits

Transmitted

1111000

1 bit

111000

2 bits

11000

3 bits

1000

4 bits

5 bits

The serial data stream sent by the transmitter for the six bits/character with parity case is

shown below in Figure 4–9. All the unused bits are ignored by the transmit logic except in

the case of five bits per character.

Data Flow

Figure 4–9. Six Bits/Character with Parity

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