CD00001237 datasheet(66/105 Pages) STMICROELECTRONICS

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ST6215C ST6225C

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OPERATING CONDITIONS (Cont’d)

11.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fOSC, and TA.

Notes:

1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.

2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.

3. Data based on characterization results, not tested in production.

Figure 39. LVD Threshold Versus VDD and fOSC

Figure 40. Typical LVD Thresholds Versus

Temperature for OTP devices

Figure

41.

Typical

LVD

thresholds

vs.

Temperature for ROM devices

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

VIT+

Reset release threshold

(VDD rise)

3.9

4.1

4.3

VIT-

Reset generation threshold

(VDD fall)

3.6

3.8

Vhys

LVD voltage threshold hysteresis

VIT+-VIT-

300

700

VtPOR

VDD rise time rate

mV/s

tg(VDD)

Filtered glitch delay on VDD

Not detected by the LVD

fOSC [MHz]

SUPPLY

2.5

3.5

4.5

5.5

FUNCTIONAL AREA

RESET

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

VIT-≥3.6

DEVICE UNDER

IN THIS AREA

VOLTAGE [V]

-40°C

25°C

95°C

125°C

T [°C]

3.6

3.8

4.2

Thresholds [V]

Vdd up

Vdd down

VIT+

VIT-

-40°C

25°C

95°C

125°C

T [°C]

3.6

3.8

4.2

Thresholds [V]

Vdd up

Vdd down

VIT+

VIT-

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