CD00001237 datasheet(44/105 Pages) STMICROELECTRONICS

44 / 105 page

ST6215C ST6225C

44/105

WATCHDOG TIMER (Cont’d)

9.1.3 Functional Description

The watchdog activation is selected through an

option in the option bytes:

– HARDWARE Watchdog option

After reset, the watchdog is permanently active,

the C bit in the WDGR is forced high and the user

can not change it. However, this bit can be read

equally as 0 or 1.

– SOFTWARE Watchdog option

After reset, the watchdog is deactivated. The func-

tion is activated by setting C bit in the WDGR reg-

ister. Once activated, it cannot be deactivated.

The counter value stored in the WDGR register

(bits SR:T0), is decremented every 3072 clock cy-

cles. The length of the timeout period can be pro-

grammed by the user in 64 steps of 3072 clock cy-

cles.

If the watchdog is activated (by setting the C bit)

and when the SR bit is cleared, the watchdog initi-

ates a reset cycle pulling the reset pin low for typi-

cally 500ns.

The application program must write in the WDGR

tion to prevent an MCU reset. The value to be

stored in the WDGR register must be between

FEh and 02h (see Table 11). To run the watchdog

function the following conditions must be true:

– The C bit is set (watchdog activated)

– The SR bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of decre-

ments which represent the time delay before the

watchdog produces a reset.

Table 11. Watchdog Timing (fOSC = 8 MHz)

9.1.3.1 Software Reset

The SR bit can be used to generate a software re-

set by clearing the SR bit while the C bit is set.

9.1.4 Recommendations

1. The Watchdog plays an important supporting

role in the high noise immunity of ST62xx devices,

and should be used wherever possible. Watchdog

related options should be selected on the basis of

a trade-off between application security and STOP

mode availability (refer to the description of the

WDACT and EXTCNTL bits on the Option Bytes).

When STOP mode is not required, hardware acti-

vation without EXTERNAL STOP MODE CON-

TROL should be preferred, as it provides maxi-

mum security, especially during power-on.

When STOP mode is required, hardware activa-

tion and EXTERNAL STOP MODE CONTROL

should be chosen. NMI should be high by default,

to allow STOP mode to be entered when the MCU

is idle.

The NMI pin can be connected to an I/O line (see

Figure 26) to allow its state to be controlled by soft-

ware. The I/O line can then be used to keep NMI

low while Watchdog protection is required, or to

avoid noise or key bounce. When no more

processing is required, the I/O line is released and

the device placed in STOP mode for lowest power

consumption.

Figure 26. A typical circuit making use of the

EXERNAL STOP MODE CONTROL feature

2. When software activation is selected (WDACT

bit in Option byte) and the Watchdog is not activat-

ed, the downcounter may be used as a simple 7-

bit timer (remember that the bits are in reverse or-

der).

The software activation option should be chosen

only when the Watchdog counter is to be used as

a timer. To ensure the Watchdog has not been un-

expectedly activated, the following instructions

should be executed:

jrr 0, WDGR, #+3 ; If C=0,jump to next

ldi WDGR, 0FDH

; SR=0 -> reset

WDGR Register

initial value

WDG timeout period

(ms)

Max.

FEh

24.576

Min.

02h

0.384

NMI

SWITCH

I/O

VR02002

CD00001237 数据表(PDF) 44 Page - STMicroelectronics

CD00001237 数据表(HTML) 44 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载