CD00001237 datasheet(42/105 Pages) STMICROELECTRONICS

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ST6215C ST6225C

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I/O PORTS (Cont’d)

8.5 REGISTER DESCRIPTION

DATA REGISTER (DR)

Port x Data Register

DRx with x = A, B or C.

Addresses 0C0h, 0C1h and 0C2h- Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = DR[7:0] Data register bits.

Reading the DR register returns either the DR reg-

ister latch content (pin configured as output) or the

digital value applied to the I/O pin (pin configured

as input).

Caution: In input mode, modifying this register will

modify the I/O port configuration (see Table 8).

Do not use the Single bit instructions on I/O port

data registers. See (Section 8.2.5).

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register

DDRx with x = A, B or C.

Addresses: 0C4h, 0C5h and 0C6h - Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = DDR[7:0] Data direction register bits.

The DDR register gives the input/output direction

configuration of the pins. Each bit is set and

cleared by software.

0: Input mode

1: Output mode

OPTION REGISTER (OR)

Port x Option Register

ORx with x = A, B or C.

Addresses: 0CCh, 0CDh and 0CEh - Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = OR[7:0] Option register bits.

The OR register allows to distinguish in output

mode if the push-pull or open drain configuration is

selected.

Output mode:

0: Open drain output(with P-Buffer deactivated)

1: Push-pull Output

Input mode: See Table 8.

Each bit is set and cleared by software.

Caution: Modifying this register, will also modify

the I/O port configuration in input mode. (see Ta-

ble 8).

Table 10. I/O Port Register Map and Reset Values

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0

OR7

OR6

OR5

OR4

OR3

OR2

OR1

OR0

Address

(Hex.)

Label

765

4321

Reset Value

of all I/O port registers

000

0000

0C0h

DRA

MSB

LSB

0C1h

DRB

0C2h

DRC

0C4h

DDRA

MSB

LSB

0C5h

DDRB

0C6h

DDRC

0CCh

ORA

MSB

LSB

0CDh

ORB

0CEh

ORC

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