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CD00001237 数据表(PDF) 12 Page - STMicroelectronics |
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CD00001237 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 105 page  ST6215C ST6225C 12/105 MEMORY MAP (Cont’d) Table 2. Hardware Register Map Legend: x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s) in the register. Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always be kept at their reset value. 3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured in input mode (refer to Section 8 "I/O PORTS" on page 38 for more details). Address Block Register Label Register Name Reset Status Remarks 080h to 083h CPU X,Y,V,W X,Y index registers V,W short direct registers xxh R/W 0C0h 0C1h 0C2h I/O Ports DRA 1) 2) 3) DRB 1) 2) 3) DRC 1) 2) 3) Port A Data Register Port B Data Register Port C Data Register 00h 00h 00h R/W R/W R/W 0C3h Reserved (1 Byte) 0C4h 0C5h 0C6h I/O Ports DDRA 2) DDRB 2) DDRC 2) Port A Direction Register Port B Direction Register Port C Direction Register 00h 00h 00h R/W R/W R/W 0C7h Reserved (1 Byte) 0C8h CPU IOR Interrupt Option Register xxh Write-only 0C9h ROM DRWR Data ROM Window register xxh Write-only 0CAh 0CBh Reserved (2 Bytes) 0CCh 0CDh 0CEh I/O Ports ORA 2) ORB 2) ORC 2) Port A Option Register Port B Option Register Port C Option Register 00h 00h 00h R/W R/W R/W 0CFh Reserved (1 byte) 0D0h 0D1h ADC ADR ADCR A/D Converter Data Register A/D Converter Control Register xxh 40h Read-only Ro/Wo 0D2h 0D3h 0D4h Timer1 PSCR TCR TSCR Timer 1 Prescaler Register Timer 1 Counter Register Timer 1 Status Control Register 7Fh 0FFh 00h R/W R/W R/W 0D5h to 0D7h Reserved (3 Bytes) 0D8h Watchdog Timer WDGR Watchdog Register 0FEh R/W 0D9h to 0FEh Reserved (38 Bytes) 0FFh CPU A Accumulator xxh R/W 1 |
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