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STM32F103CBU6 数据表(PDF) 79 Page - STMicroelectronics |
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STM32F103CBU6 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 105 page  DocID13587 Rev 16 79/105 STM32F103x8, STM32F103xB Electrical characteristics 104 Figure 38. Typical connection diagram using the ADC 1. Refer to Table 46 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 39 or Figure 40, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. ai14150c STM32F103xx VDD AINx IL±1 µA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) 12-bit converter CADC(1) Sample and hold ADC converter VREF+ (see note 1) STM32F103xx VDDA VSSA /VREF– (see note 1) 1 µF // 10 nF 1 µF // 10 nF ai14388b |
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